参数资料
型号: AD73322AR
厂商: ANALOG DEVICES INC
元件分类: 通信及网络
英文描述: Low Cost, Low Power CMOS General-Purpose Dual Analog Front End
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO28
封装: SOIC-28
文件页数: 29/40页
文件大小: 437K
代理商: AD73322AR
REV. 0
AD73322L
–29–
CONTINUOUS
TIME
LOW-PASS
FILTER
V
REF
VFBN1
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
AD73322L
V
REF
+6/
15dB
PGA
REFERENCE
0/38dB
PGA
GAIN
1
C1
R2
R1
C2
R
B
R
A
5V
ELECTRET
PROBE
10 F
C
REFCAP
Figure 30. Electret Microphone Interface Circuit
Analog Output
The AD73322L
s differential analog output (VOUT) is produced
by an on-chip differential amplifier. The differential output can
be ac-coupled or dc-coupled directly to a load which can be a
headset or the input of an external amplifier (the specified mini-
mum resistive load on the output section is 150
.) It is possible
to connect the outputs in either a differential or a single-ended
configuration but please note that the effective maximum output
voltage swing (peak to peak) is halved in the case of single-ended
connection. Figure 31 shows a simple circuit providing a differen-
tial output with ac coupling. The capacitors in this circuit (C
OUT
)
are optional; if used, their value can be chosen as follows:
C
f R
OUT
LOAD
=
1
2
π
where
f
C
= desired cutoff frequency.
VFBN1
GAIN
1
V
REF
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
REFERENCE
C
REFCAP
C
OUT
C
OUT
+6/
15dB
PGA
COTIME
LOW-PASS
FILTER
AD73322L
R
LOAD
Figure 31. Example Circuit for Differential Output
Figure 32 shows an example circuit for providing a single-ended
output with ac coupling. The capacitor of this circuit (C
OUT
) is
not optional if dc current drain is to be avoided.
VFBN1
GAIN
1
V
REF
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
REFERENCE
C
OUT
0.1 F
+6/
15dB
PGA
CONTIME
LFILTER
AD73322L
R
LOAD
Figure 32. Example Circuit for Single-Ended Output
Differential to Single-Ended Output
In some applications it may be desirable to convert the full
differential output of the decoder channel to a single-ended
signal. The circuit of Figure 33 shows a scheme for doing this.
VFBN1
GAIN
1
V
REF
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
REFERENCE
V
REF
0/38dB
PGA
R
LOAD
R
I
R
I
R
F
R
F
0.1 F
+6/
15dB
CONTIME
LFILTER
AD73322L
Figure 33. Example Circuit for Differential to Single-
Ended Output Conversion
Digital Interfacing
The AD73322L is designed to easily interface to most common
DSPs. The SCLK, SDO, SDOFS, SDI and SDIFS must be
connected to the DSP
s Serial Clock, Receive Data, Receive
Data Frame Sync, Transmit Data and Transmit Data Frame
Sync pins respectively. The SE pin may be controlled from a
parallel output pin or flag pin such as FL0-2 on the ADSP-21xx
(or XF on the TMS320C5x) or, where SPORT power-down is not
required, it can be permanently strapped high using a suitable
pull-up resistor. The
RESET
pin may be connected to the sys-
tem hardware reset structure or it may also be controlled using a
dedicated control line. In the event of tying it to the global sys-
tem reset, it is advisable to operate the device in mixed mode,
which allows a software reset, otherwise there is no convenient
way of resetting the device. Figures 34 and 35 show typical
connections to an ADSP-218x and TMS320C5x respectively.
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