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参数资料
| 型号： | AD73322AR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 18/40页 |
| 文件大小： | 437K |
| 代理商： | AD73322AR |
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REV. 0
AD73322L
–18–
Table XIII. Control Register A Description
CONTROL REGISTER A
7
6
5
4
3
2
1
0
T
E
S
E
R
2
C
D
1
C
D
0
C
D
B
L
S
B
L
D
M
M
/
A
M
T
A
G
P
D
Bit
Name
Description
0
1
2
3
4
5
6
7
DATA/
PGM
MM
DLB
SLB
DC0
DC1
DC2
RESET
Operating Mode (0 = Program; 1 = Data Mode)
Mixed Mode (0 = Off; 1 = Enabled)
Digital Loop-Back Mode (0 = Off; 1 = Enabled)
SPORT Loop-Back Mode (0 = Off; 1 = Enabled)
Device Count (Bit 0)
Device Count (Bit 1)
Device Count (Bit 2)
Software Reset (0 = Off; 1 = Initiates Reset)
Table XIV. Control Register B Description
CONTROL REGISTER B
7
6
5
4
3
2
1
0
—
U
R
F
E
R
U
P
C
A
D
U
P
C
D
A
U
P
A
I
U
P
T
G
A
U
P
U
P
Bit
Name
Description
0
1
2
3
4
5
6
7
DIR0
DIR1
SCD0
SCD1
MCD0
MCD1
MCD2
CEE
Decimation/Interpolation Rate (Bit 0)
Decimation/Interpolation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = Off; 1 = Enabled)
Table XV. Control Register C Description
CONTROL REGISTER C
7
6
5
4
3
2
1
0
E
T
U
M
2
S
G
O
1
S
G
O
0
S
G
O
D
O
M
R
2
S
G
I
1
S
G
I
0
S
G
I
Bit
Name
Description
0
1
2
3
4
5
6
7
PU
PUAGT
PUIA
PUADC
PUDAC
PUREF
RU
—
Power-Up Device (0 = Power-Down; 1 = Power On)
Analog Gain Tap Power (0 = Power-Down; 1 = Power On)
Input Amplifier Power (0 = Power-Down; 1 = Power On)
ADC Power (0 = Power-Down; 1 = Power On)
DAC Power (0 = Power-Down; 1 = Power On)
REF Power (0 = Power-Down; 1 = Power On)
REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
Reserved, must be programmed to 0.
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| AD73322AR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R |
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