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参数资料
| 型号： | AD73460BB-40 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | Six-Input Channel Analog Front End |
| 中文描述： | 24-BIT, 26 MHz, OTHER DSP, PBGA119 |
| 封装： | PLASTIC, CHIP SCALE, BGA-119 |
| 文件页数： | 12/32页 |
| 文件大小： | 290K |
| 代理商： | AD73460BB-40 |
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REV. 0
AD73460
–12–
Analog Sigma-Delta Modulator
The AD73460 input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73460, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to f
S
/2 = DMCLK/16
(Figure 3a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 3b). The combina-
tion of these techniques, followed by the application of a digital
filter, reduces the noise in band sufficiently to ensure good
dynamic performance from the part (Figure 3c).
BAND
OF
INTEREST
f
/2
DMCLK/16
a.
f
S
/2
DMCLK/16
NOISE-SHAPING
b.
BAND
OF
INTEREST
f
/2
DMCLK/16
DIGITAL FILTER
BAND
OF
INTEREST
c.
Figure 3. Sigma-Delta Noise Reduction
Figure 4 shows the various stages of filtering that are employed
in a typical AD73460 application. In Figure 4a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling frequency.
This also shows the major difference between the initial over-
sampling rate and the bandwidth of interest. In Figure 4b, the
signal and noise-shaping responses of the sigma-delta modulator
are shown. The signal response provides further rejection of any
high frequency signals while the noise-shaping will push the inher-
ent quantization noise to an out-of-band position. The detail of
Figure 4c shows the response of the digital decimation filter
(Sinc-cubed response) with nulls every multiple of DMCLK/256,
which is the decimation filter update rate. The final detail in
Figure 4d shows the application of a final antialias filter in the
DSP engine. This has the advantage of being implemented accord-
ing to the user
’
s requirements and available MIPS. The filtering
in Figures 4a through 4c is implemented in the AD73460.
f
B
= 4kHz
f
SINIT
= DMCLK/8
a. Analog Antialias Filter Transfer Function
f
B
= 4kHz
f
SINIT
= DMCLK/8
NOISE TRANSFER FUNCTION
SIGNAL TRANSFER FUNCTION
b. Analog Sigma-Delta Modulator Transfer Function
f
B
= 4kHz
f
SINTER
= DMCLK/256
c. Digital Decimator Transfer Function
f
B
= 4kHz
f
SINTER
= DMCLK/256
f
SFINAL
= 8kHz
d. Final Filter LPF (HPF) Transfer Function
Figure 4. DC Frequency Responses
Decimation Filter
The digital filter used in the AD73460 carries out two important
functions. Firstly, it removes the out-of-band quantization noise,
which is shaped by the analog modulator and secondly, it deci-
mates the high frequency bitstream to a lower rate 15-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/256,
and increases the resolution from a single bit to 15 bits. Its Z
transform is given as: [(1
–
Z
–
32
)/(1
–
Z
–
1
)]
3
. This ensures a mini-
mal group delay of 25
μ
s.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73460BB-80 | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:6-CHADC WITH DSP I.C. - Bulk |
| AD7346ASTZ | 制造商:Analog Devices 功能描述: |
| AD7346ASTZ-RL | 功能描述:IC ANALOG FRONT END 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| AD7346B | 制造商:AD 制造商全称:Analog Devices 功能描述:2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| AD734AN | 功能描述:IC MULTIPLIER/DIVIDER 14-DIP RoHS:否 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
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