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参数资料
| 型号： | AD73460BB-40 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | Six-Input Channel Analog Front End |
| 中文描述： | 24-BIT, 26 MHz, OTHER DSP, PBGA119 |
| 封装： | PLASTIC, CHIP SCALE, BGA-119 |
| 文件页数： | 31/32页 |
| 文件大小： | 290K |
| 代理商： | AD73460BB-40 |
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AD73460
–31–
REV. 0
CASCADE OPERATION
Where it is required to configure an extra analog input channels
to the existing six channels on the AD73460 it is possible to
cascade six more channels (using external AD73360 AFEs) by
using the scheme described in Figure 22. It is necessary how-
ever to ensure that the timing of the SE and
ARESET
signals is
synchronized at each device in the cascade. A simple D-type
flip-flop is sufficient to synchronize each signal to the master
clock AMCLK as shown in Figure 21.
1/2
74HC74
CLK
D
Q
DSP CONTROL
TO SE
AMCLK
SE SIGNAL SYNCHRONIZED
TO AMCLK
1/2
74HC74
CLK
D
Q
DSP CONTROL
TO
ARESET
AMCLK
ARESET
SIGNAL SYNCHRONIZED
TO AMCLK
Figure 21. SE and
ARESET
Sync Circuit for Cascaded
Operation
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the serial clock
rate chosen. The formula below gives an indication of whether
the combination of sample rate, and serial clock can be success-
fully cascaded. This assumes a directly coupled frame sync
arrangement as shown in Figure 20 and does not take any interrupt
latency into account.
1
f
S
6
1
16
17
Device Count
SCLK
≥
×
×
+
[((
)
)
]
When using the indirectly coupled frame sync configuration in
cascaded operation it is necessary to be aware of the restrictions
in sending control word data to all devices in the cascade. The
user should ensure that there is sufficient time for all the control
words to be sent between reading the last ADC sample and the
start of the next sample period.
Connection of a cascade, as shown in Figure 22, is no more
complicated than connecting a single device. Instead of connect-
ing the SDO and SDOFS to the DSP
’
s Rx port, these are now
daisy-chained to the SDI and SDIFS of the next device in the
cascade. The SDO and SDOFS of the final device in the cascade
are connected to the DSP
’
s Rx port to complete the cascade. SE
and
ARESET
on all devices are fed from the signals that were
synchronized with the AMCLK using the circuit of Figure 21.
The SCLK from only one device need be connected to the DSP
’
s
SCLK input(s) as both devices will be running at the same SCLK
frequency and phase.
TFS
DT
DR
RFS
AFE
SDIFS
SDI
SCLK
SDO
SDOFS
SCLK
DEVICE 1
AMCLK
SE
ARESET
ADDITIONAL
AD73360
AFE
74HC74
Q0
Q1
D1
D0
FL0
FL1
DSP
SECTION
CLK
SDIFS
SDI
SCLK
SDO
SDOFS
DEVICE 2
MCLK
SE
RESET
AD73460
Figure 22. Connection of an AD73360 Cascaded to the
AD73460
Interfacing to the AFE
’
s Analog Inputs
The AD73460 features six signal conditioning inputs. Each
signal conditioning block allows the AD73460 to be used with
either a single-ended or differential signal. The applied signal
can also be inverted internally by the AD73460 if required. The
analog input signal to the AD73460 can be dc-coupled, pro-
vided that the dc bias level of the input signal is the same as the
internal reference level (REFOUT). Figure 23 shows the recom-
mended differential input circuit for the AD73460. The circuit
of Figure 23 implements first-order low-pass filters with a 3 dB
point at 34 kHz; these are the only filters that must be imple-
mented external to the AD73460 to prevent aliasing of the
sampled signal. Since the ADC uses a highly oversampled
approach that transfers the bulk of the antialiasing filtering into
the digital domain, the off-chip antialiasing filter need only be of
a low order. It is recommended that for optimum performance
the capacitors used for the antialiasing filter be of high quality
dielectric (NPO).
VIN
TO INPUT BIAS
CIRCUITRY
VINPx
VINNx
REFOUT
REFCAP
VOLTAGE
REFERENCE
0.047 F
0.047 F
100
100
0.1 F
Figure 23. Example Circuit for Differential Input
(DC Coupling)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73460BB-80 | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:6-CHADC WITH DSP I.C. - Bulk |
| AD7346ASTZ | 制造商:Analog Devices 功能描述: |
| AD7346ASTZ-RL | 功能描述:IC ANALOG FRONT END 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| AD7346B | 制造商:AD 制造商全称:Analog Devices 功能描述:2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| AD734AN | 功能描述:IC MULTIPLIER/DIVIDER 14-DIP RoHS:否 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
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