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参数资料
| 型号： | AD7658BSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 6CH 250KSPS 64LQFP |
| 标准包装： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行，并联 |
| 转换器数目： | 6 |
| 功率耗散（最大）： | 143mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 6 个单端，双极 |
| 产品目录页面： | 778 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7658CBZ-ND - BOARD EVAL FOR AD7658 |
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AD7656/AD7657/AD7658
Data Sheet
Rev. D | Page 12 of 32
Pin No.
Mnemonic
Description
19
CS
Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low
in parallel mode, the output bus is enabled and the conversion result is output on the parallel data
bus lines. When both CS and WR are logic low in parallel mode, DB[15:8] are used to write data to
the on-chip control register. In serial mode, the CS is used to frame the serial read transfer and clock
out the MSB of the serial output data.
20
RD
Read Data. When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial
mode, the RD line should be held low.
63
WR/REFEN/DIS
Write Data/Reference Enable/Disable. When H/S SEL pin is high and both CS and WR are logic low,
DB[15:8] are used to write data to the internal control register. When the H/S SEL pin is low, this pin
is used to enable or disable the internal reference. When H/S SEL = 0 and REFEN/DIS = 0, the internal
reference is disabled and an external reference should be applied to the REFIN/REFOUT pin. When
H/S SEL = 0 and REFEN/DIS = 1, the internal reference is enabled and the REFIN/REFOUT pin should be
decoupled. See the Reference Section.
18
BUSY
BUSY Output. This pin transitions high when a conversion is started and remains high until the
conversion is complete and the conversion data is latched into the output data registers. A new
conversion should not be initiated on the AD7656/AD7657/AD7658 when the BUSY signal is high.
51
REFIN/REFOUT
Reference Input/Output. The on-chip reference is available on this pin for use external to the
AD7656/AD7657/AD7658. Alternatively, the internal reference can be disabled and an external
reference can be applied to this input. See the Reference Section. When the internal reference is
enabled, this pin should be decoupled using at least a 10 F decoupling capacitor.
61
SER/PAR/SEL
Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this
pin is high, the serial interface mode is selected. In serial mode, DB[10:8] take on their DOUT[C:A]
function, DB[0:2] take on their DOUT select function, DB7 takes on its DCEN function. In serial mode,
DB15 and DB[13:11] should be tied to DGND.
17
DB0/SEL A
Data Bit 0/Select DOUT A. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin.
When SER/PAR = 1, this pin takes on its SEL A function; it is used to configure the serial interface. If
this pin is 1, the serial interface operates with one/two/three DOUT output pins and enables DOUT A
as a serial output. When operating in serial mode, this pin should always be = 1.
16
DB1/SEL B
Data Bit 1/Select DOUT B. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin.
When SER/PAR = 1, this pin takes on its SEL B function; it is used to configure the serial interface. If
this pin is 1, the serial interface operates with two/three DOUT output pins and enables DOUT B as a
serial output. If this pin is 0, the DOUT B is not enabled to operate as a serial data output pin and
only one DOUT output pin, DOUT A, is used. Unused serial DOUT pins should be left unconnected.
15
DB2/SEL C
Data Bit 2/Select DOUT C. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin.
When SER/PAR = 1, this pin takes on its SEL C function; it is used to configure the serial interface. If
this pin is 1, the serial interface operates with three DOUT output pins and enables DOUT C as a
serial output. If this pin is 0, the DOUT C is not enabled to operate as a serial data output pin.
Unused serial DOUT pins should be left unconnected.
14
DB3/DCIN C
Data Bit 3/Daisy-Chain Input C. When SER/PAR = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input C. When operating
in serial mode but not in daisy-chain mode, this pin should be tied to DGND.
13
DB4/DCIN B
Data Bit 4/Daisy-Chain Input B. When SER/PAR = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input B. When operating
in serial mode but not in daisy-chain mode, this pin should be tied to DGND.
12
DB5/DCIN A
Data Bit 5/Daisy-Chain Input A. When SER/PAR is low, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input A. When operating
in serial mode but not in daisy-chain mode, this pin should be tied to DGND.
11
DB6/SCLK
Data Bit 6/Serial Clock. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When
SER/PAR = 1, this pin takes on its SCLK input function; it is the read serial clock for the serial transfer.
10
DB7/HBEN/DCEN
Data Bit 7/High Byte Enable/Daisy-Chain Enable. When operating in parallel word mode
(SER/PAR = 0 and W/B = 0), this pin takes on its Data Bit 7 function. When operating in parallel
byte mode (SER/PAR = 0 and W/B = 1), this pin takes on its HBEN function. When in this mode and
the HBEN pin is logic high, the data is output MSB byte first on DB[15:8]. When the HBEN pin is
logic low, the data is output LSB byte first on DB[15:8]. When operating in serial mode (SER/PAR = 1),
this pin takes on its DCEN function. When the DCEN pin is logic high, the parts operate in daisy-
chain mode with DB[5:3] taking on their DCIN[A:C] function. When operating in serial mode but
not in daisy-chain mode, this pin should be tied to DGND.
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