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参数资料
| 型号： | AD7685CRMZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT PSEUDO-DIFF 10MSOP |
| 产品培训模块： | Power Line Monitoring Motor Control |
| 设计资源： | Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130) |
| 标准包装： | 1,000 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 250k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 15mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个伪差分，单极 |
| 配用： | EVAL-AD7685CBZ-ND - BOARD EVAL FOR AD7685 |
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AD7685
Rev. C | Page 19 of 28
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7685 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7685 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
DATA IN
IRQ
CLK
CONVERT
VIO
DIGITAL HOST
02
96
8-
0
34
47k
CNV
SCK
SDO
SDI
VIO
AD7685
Figure 36. CS Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
SDO
D15
D14
D1
D0
tDIS
SCK
1
2
3
15
16
17
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
tCNVH
tACQ
ACQUISITION
SDI = 1
0
29
68
-03
5
Figure 37. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7685-C-U2 | 制造商:Analog Devices 功能描述:250 KSPS 16-BIT PULSAR? A/D CONVERTER IN ?SOIC - Bulk |
| AD7685-S-U2 | 制造商:Analog Devices 功能描述:250 KSPS 16-BIT PULSAR? A/D CONVERTER - Bulk |
| AD7685XRM-U3 | 制造商:Analog Devices 功能描述:A/D CONVERTER 250KSPS 16-BIT PULSAR - Bulk |
| AD7686 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR Differential ADC in MSOP/QFN |
| AD76861 | 制造商:AD 制造商全称:Analog Devices 功能描述:18-Bit, 2 MSPS PulSAR 15 mW ADC in LFCSP (QFN) |
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