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参数资料
| 型号： | IDT71T75602S133PFI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/23页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 18MBIT 133MHZ 100TQFP |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 ZBT |
| 存储容量： | 18M（512K x 36） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 71T75602S133PFI8 |
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT? SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Burst Read Operation (1)
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
Address
A 0
X
X
X
X
A 1
X
X
A 2
R/ W
H
X
X
X
X
H
X
X
H
ADV/ LD
L
H
H
H
H
L
H
H
L
CE (2)
L
X
X
X
X
L
X
X
L
CEN
L
L
L
L
L
L
L
L
L
BW x
X
X
X
X
X
X
X
X
X
OE
X
X
L
L
L
L
L
L
L
I/O
X
X
Q 0
Q 0+1
Q 0+2
Q 0+3
Q 0
Q 1
Q 1+1
Comments
Address and Control meet setup
Clock Setup Valid, Advance Counter
Address A 0 Read Out, Inc. Count
Address A 0+1 Read Out, Inc. Count
Address A 0+2 Read Out, Inc. Count
Address A 0+3 Read Out, Load A 1
Address A 0 Read Out, Inc. Count
Address A 1 Read Out, Inc. Count
Address A 1+1 Read Out, Load A 2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE 1 = L, CE 2 = L and CE 2 = H. CE = H is defined as CE 1 = H, CE 2 = H or CE 2 = L.
Write Operation (1)
5313 tbl 14
Cycle
n
n+1
n+2
Address
A 0
X
X
R/ W
L
X
X
ADV/ LD
L
X
X
CE (2)
L
X
X
CEN
L
L
L
BW x
L
X
X
OE
X
X
X
I/O
X
X
D 0
Comments
Address and Control meet setup
Clock Setup Valid
Write to Address A 0
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE 1 = L, CE 2 = L and CE 2 = H. CE = H is defined as CE 1 = H, CE 2 = H or CE 2 = L.
Burst Write Operation (1)
5313 tbl 15
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
Address
A 0
X
X
X
X
A 1
X
X
A 2
R/ W
L
X
X
X
X
L
X
X
L
ADV/ LD
L
H
H
H
H
L
H
H
L
CE (2)
L
X
X
X
X
L
X
X
L
CEN
L
L
L
L
L
L
L
L
L
BW x
L
L
L
L
L
L
L
L
L
OE
X
X
X
X
X
X
X
X
X
I/O
X
X
D 0
D 0+1
D 0+2
D 0+3
D 0
D 1
D 1+1
Comments
Address and Control meet setup
Clock Setup Valid, Inc. Count
Address A 0 Write, Inc. Count
Address A 0+1 Write, Inc. Count
Address A 0+2 Write, Inc. Count
Address A 0+3 Write, Load A 1
Address A 0 Write, Inc. Count
Address A 1 Write, Inc. Count
Address A 1+1 Write, Load A 2
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE 1 = L, CE 2 = L and CE 2 = H. CE = H is defined as CE 1 = H, CE 2 = H or CE 2 = L.
10
6.42
5313 tbl 16
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