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参数资料
| 型号： | IDT71T75602S133PFI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/23页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 18MBIT 133MHZ 100TQFP |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步 ZBT |
| 存储容量： | 18M（512K x 36） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 71T75602S133PFI8 |
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT? SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Configuration — 1Mx 18
Absolute Maximum Ratings (1)
Symbol
Rating
Commercial
Industrial
Unit
V TERM
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
(2)
Terminal Voltage with
Respect to GND
-0.5 to +3.6
-0.5 to +3.6
V
NC
NC
NC
V DDQ
V SS
NC
NC
I/O 8
I/O 9
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
A 10
NC
NC
V DDQ
V SS
NC
I/O P1
I/O 7
I/O 6
V TERM (3,6)
V TERM (4,6)
V TERM (5,6)
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
-0.5 to V DD
-0.5 to V DD +0.5
-0.5 to V DDQ +0.5
-0.5 to V DD
-0.5 to V DD +0.5
-0.5 to V DDQ +0.5
V
V
V
V SS
V DDQ
I/O 10
I/O 11
V DD (1)
V DD
V DD (1)
V SS
10
11
12
13
14
15
16
17
71
70
69
68
67
66
65
64
V SS
V DDQ
I/O 5
I/O 4
V SS
V DD (1)
V DD
ZZ
T A (7)
T BIAS
T STG
Operating Ambient
Temperature
Temperature Under Bias
Storage Temperature
0 to +70
-55 to +125
-55 to +125
-40 to +85
-55 to +125
-55 to +125
o
o
o
C
C
C
I/O 12
I/O 13
V DDQ
V SS
18
19
20
21
63
62
61
60
I/O 3
I/O 2
V DDQ
V SS
P T
I OUT
Power Dissipation
DC Output Current
2.0
50
2.0
50
W
mA
I/O 14
I/O 15
I/O P2
NC
V SS
V DDQ
NC
NC
22
23
24
25
26
27
28
29
59
58
57
56
55
54
53
52
I/O 1
I/O 0
NC
NC
V SS
V DDQ
NC
NC
,
5313 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
NC
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
51
NC
5313 drw 02a
maximum rating conditions for extended periods may affect reliability.
2. V DD terminals only.
3. V DDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
100 TQFP
Top View
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to V DD as long as the
input voltage is ≥ V IH .
2. Pins 38, 39 and 43 will be pulled internally to V DD if not actively driven. To
disable the TAP controller without interfering with normal operation, several
settings are possible. Pins 38, 39 and 43 could be tied to V DD or V SS and pin 42
should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38,
39 and 43 could be left unconnected “NC” and the JTAG circuit will remain
disabled from power up.
3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin
TQFP package for the 36M ZBT device.
100-Pin TQFP Capacitance
(T A = +25°C, f = 1.0MHz)
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary; however,
the voltage on any input or I/O pin cannot exceed V DDQ during power supply ramp
up.
7. During production testing, the case temperature equals T A .
165 fBGA Capacitance
(T A = +25°C, f = 1.0MHz)
Symbol
C IN
C I/O
Parameter (1)
Input Capacitance
I/O Capacitance
Conditions
V IN = 3dV
V OUT = 3dV
Max.
5
7
Unit
pF
pF
Symbol
C IN
C I/O
Parameter (1)
Input Capacitance
I/O Capacitance
Conditions
V IN = 3dV
V OUT = 3dV
Max.
7
7
Unit
pF
pF
119 BGA Capacitance
(T A = +25°C, f = 1.0MHz)
5313 tbl 07
5313 tbl 07b
Symbol
C IN
C I/O
Parameter (1)
Input Capacitance
I/O Capacitance
Conditions
V IN = 3dV
V OUT = 3dV
Max.
7
7
Unit
pF
pF
5313 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
5
6.42
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