参数资料
| 型号： | AD7710AQ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT DIFF INP 24-CDIP |
| 标准包装： | 15 |
| 位数： | 24 |
| 采样率（每秒）： | 1.03k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 45mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 24-CDIP（0.300"，7.62mm） |
| 供应商设备封装： | 24-CDIP |
| 包装： | 管件 |
| 输入数目和类型： | 2 个差分，单极；2 个差分，双极 |
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REV. G
–18–
AD7710
performed; the VREF node is then switched in and another conver-
sion is performed. When the calibration sequence is complete, the
calibration coefficients updated, and the filter resettled to the ana-
log input voltage, the
DRDY output goes low. The self-calibration
procedure takes into account the selected gain on the PGA.
For bipolar input ranges in the self-calibrating mode, the
sequence is very similar to that just outlined. In this case, the
two points that the AD7710 calibrates are midscale (bipolar
zero) and positive full scale.
System Calibration
System calibration allows the AD7710 to compensate for
system gain and offset errors as well as its own internal errors.
System calibration performs the same slope factor calculations
as self-calibration but uses voltage values presented by the sys-
tem to the AIN inputs for the zero- and full-scale points. System
calibration is a two-step process. The zero-scale point must be
presented to the converter first. It must be applied to the con-
verter before the calibration step is initiated and remain stable
until the step is complete. System calibration is initiated by
writing the appropriate values (0, 1, 0) to the MD2, MD1,
MD0 bits of the control register. The
DRDY output from the
device will signal when the step is complete by going low. After
the zero-scale point is calibrated, the full-scale point is applied,
and the second step of the calibration process is initiated by
again writing the appropriate values (0, 1, 1) to MD2, MD1,
MD0. Again the full-scale voltage must be set up before the
calibration is initiated, and it must remain stable throughout the
calibration step.
DRDY goes low at the end of this second step
to indicate that the system calibration is complete. In the uni-
polar mode, the system calibration is performed between the
two endpoints of the transfer function; in the bipolar mode, it is
performed between midscale and positive full scale.
This two-step system calibration mode offers another feature.
After the sequence has been completed, additional offset or gain
calibrations can be performed by themselves to adjust the zero
reference point or the system gain. This is achieved by perform-
ing the first step of the system calibration sequence (by writing
0, 1, 0 to MD2, MD1, MD0). This will adjust the zero-scale or
offset point but will not change the slope factor from that set
during a full system calibration sequence.
System calibration can also be used to remove any errors from
an antialiasing filter on the analog input. A simple R, C anti-
aliasing filter on the front end may introduce a gain error on the
analog input voltage but the system calibration can be used to
remove this error.
System Offset Calibration
System offset calibration is a variation of both the system cali-
bration and self-calibration. In this case, the zero-scale point
for the system is presented to the AIN input of the converter.
System offset calibration is initiated by writing 1, 0, 0 to MD2,
MD1, MD0. The system zero-scale coefficient is determined by
converting the voltage applied to the AIN input, while the full-
scale coefficient is determined from the span between this AIN
conversion and a conversion on VREF. The zero-scale point
should be applied to the AIN input for the duration of the cali-
bration sequence. This is a one-step calibration sequence with
DRDY going low when the sequence is completed. In unipolar
mode, the system offset calibration is performed between the
two endpoints of the transfer function; in bipolar mode, it is
performed between midscale and positive full scale.
Background Calibration
The AD7710 also offers a background calibration mode where
the part interleaves its calibration procedure with its normal
conversion sequence. In background calibration mode, the same
voltages are used as the calibration points that are used in the
self-calibration mode, that is, shorted inputs and VREF. The
background calibration mode is invoked by writing 1, 0, 1 to
MD2, MD1, MD0 of the control register. When invoked, the
background calibration mode reduces the output data rate of the
AD7710 by a factor of 6 while the –3 dB bandwidth remains
unchanged. The advantage is that the part is continually per-
forming calibration and automatically updating its calibration
coefficients. As a result, the effects of temperature drift, sup-
ply sensitivity, and time drift on zero- and full-scale errors are
automatically removed. When the background calibration mode
is turned on, the part will remain in this mode until bits MD2,
MD1, and MD0 of the control register are changed. With back-
ground calibration mode on, the first result from the AD7710
will be incorrect because the full-scale calibration will not have
been performed. For a step change on the input, the second
output update will have settled to 100% of the final value.
Table VI summarizes the calibration modes and the calibration
points associated with them. It also gives the duration from
when the calibration is invoked to when valid data is available to
the user.
Table VI. Calibration Truth Table
Cal Type
MD2, MD1, MD0
Zero-Scale Cal
Full-Scale Cal
Sequence
Duration
Self-Cal
0, 0, 1
Shorted Inputs
VREF
One Step
9
× 1/Output Rate
System Cal
0, 1, 0
AIN
Two Steps
4
× 1/Output Rate
System Cal
0, 1, 1
AIN
Two Steps
4
× 1/Output Rate
System Offset Cal
1, 0, 0
AIN
VREF
One Step
9
× 1/Output Rate
Background Cal
1, 0, 1
Shorted Inputs
VREF
One Step
6
× 1/Output Rate
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