参数资料
型号: AD7710AQ
厂商: Analog Devices Inc
文件页数: 14/32页
文件大小: 0K
描述: IC ADC 24BIT DIFF INP 24-CDIP
标准包装: 15
位数: 24
采样率(每秒): 1.03k
数据接口: 串行
转换器数目: 1
功率耗散(最大): 45mW
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 24-CDIP(0.300",7.62mm)
供应商设备封装: 24-CDIP
包装: 管件
输入数目和类型: 2 个差分,单极;2 个差分,双极
AD7710
REV. G
–21–
Read Operation
As with self-clocking mode, data can be read from either the
output register, the control register, or the calibration registers.
A0 determines whether the data read accesses data from the
control register or from the output/calibration registers. This A0
signal must remain valid for the duration of the serial read
operation. With A0 high, data is accessed from either the output
register or from the calibration registers. With A0 low, data is
accessed from the control register.
The function of the
DRDY line is dependent only on the output
update rate of the device and the reading of the output data
register.
DRDY goes low when a new data-word is available in
the output data register. It is reset high when the last bit of data
(either 16th bit or 24th bit) is read from the output register. If
data is not read from the output register, the
DRDY line will
remain low. The output register will continue to be updated at
the output update rate, but
DRDY will not indicate this. A read
from the device in this circumstance will access the most recent
word in the output register. If a new data-word becomes avail-
able to the output register while data is being read from the
output register,
DRDY will not indicate this and the new data-
word will be lost to the user.
DRDY is not affected by reading
from the control register or the calibration register.
Data can be accessed from the output data register only when
DRDY is low. If RFS goes low while DRDY is high, no data
transfer will take place.
DRDY does not have any effect on reading
data from the control register or from the calibration registers.
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the
DRDY line and does not have any effect on the status of
DRDY. A write operation to the control registers or calibration
register must always write 24 bits.
Figure 11 shows a write operation to the AD7710. A0 determines
whether a write operation transfers data to the control register or to
the calibration registers. This A0 signal must remain valid for the
duration of the serial write operation. The falling edge of
TFS
enables the internally generated SCLK output. The serial data
to be loaded to the AD7710 must be valid on the rising edge of
this SCLK signal. Data is clocked into the AD7710 on the rising
edge of the SCLK signal with the MSB transferred first. On the
last active high time of SCLK, the LSB is loaded to the AD7710.
Subsequent to the next falling edge of SCLK, the SCLK output is
turned off. (The timing diagram in Figure 11 assumes a pull-up
resistor on the SCLK line.)
External Clocking Mode
The AD7710 is configured for external clocking mode by
tying the MODE pin low. In this mode, SCLK of the AD7710
is configured as an input, and an external serial clock must be
provided to this SCLK pin. This external clocking mode is
designed for direct interface to systems that provide a serial
clock output that is synchronized to the serial data output,
including microcontrollers such as the 80C51, 87C51, 68HC11,
68HC05, and most digital signal processors.
SDATA (I)
SCLK (O)
TFS (I)
A0 (I)
t14
t15
t18
t19
t10
9
t
t16
MSB
LSB
t17
Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation
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