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参数资料
| 型号： | AD7711AQ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT RTD I SOURCE 24CDIP |
| 标准包装： | 15 |
| 位数： | 24 |
| 采样率（每秒）： | 1.03k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 52.5mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 80°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 24-CDIP（0.300"，7.62mm） |
| 供应商设备封装： | 24-CDIP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，单极；1 个单端，双极；1 个差分，单极；1 个差分，双极 |
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REV. G
–26–
AD7711
Table VIII. 8XC51 Code for Writing to the AD7711
MOV SCON,#00000000B;
Configure 8051 for MODE 0
and Enable Serial Reception
MOV IE,#10010000B;
Enable Transmit Interrupt
MOV IP,#00010000B;
Prioritize the Transmit Interrupt
SETB 91H;
Bring
TFS High
SETB 90H;
Bring
RFS High
MOV R1,#003H;
Sets Number of Bytes to Be Written
in a Write Operation
MOV R0,#030H;
Start Address in RAM for Bytes
MOV A,#00H;
Clear Accumulator
MOV SBUF,A;
Initialize the Serial Port
WAIT:
JMP WAIT;
Wait for Interrupt
INT ROUTINE:
NOP;
Interrupt Subroutine
MOV A,R1;
Load R1 to Accumulator
JZ FIN;
If Zero Jump to FIN
DEC R1;
Decrement R1 Byte Counter
MOV A,@R;
Move Byte into the Accumulator
INC R0;
Increment Address
RLC A;
Rearrange Data from LSB First
to MSB First
MOV B.0,C; RLC A; MOV B.1,C; RLC A;
MOV B.2,C; RLC A; MOV B.3,C; RLC A;
MOV B.4,C; RLC A; MOV B.5,C; RLC A;
MOV B.6,C; RLC A; MOV B.7,C; MOV A,B;
CLR 93H;
Bring A0 Low
CLR 91H;
Bring
TFS Low
MOV SBUF,A;
Write to Serial Port
RETI;
Return from Subroutine
FIN:
SETB 91H;
Set
TFS High
SETB 93H;
Set A0 High
RETI;
Return from Interrupt Subroutine
AD7711 to 68HC11 Interface
Figure 18 shows an interface between the AD7711 and the
68HC11 microcontroller. The AD7711 is configured for its
external clocking mode, while the SPI port is used on the
68HC11 is in single-chip mode. The
DRDY line from the
AD7711 is connected to the Port PC2 input of the 68HC11, so
the
DRDY line is polled by the 68HC11. The DRDY line can
be connected to the
IRQ input of the 68HC11 if an interrupt
driven system is preferred. The 68HC11 MOSI and MISO lines
should be configured for wire-OR operation. Depending on the
interface configuration, it may be necessary to provide bidirec-
tional buffers between the 68HC11 MOSI and MISO lines.
The 68HC11 is configured in the master mode with its CPOL
Logic 0 bit set to a Logic 0 and its CPHA bit set to a Logic 1.
With a 10 MHz master clock on the AD7711, the interface will
operate with all four serial clock rates of the 68HC11.
AD7711
SDATA
SCLK
A0
RFS
TFS
PC0
MISO
SCK
PC1
PC2
MODE
PC3
DRDY
SYNC
68HC11
MOSI
SS
DVDD
Figure 18. AD7711 to 68HC11 Interface
APPLICATIONS
4-Wire RTD Configurations
Figure 19 shows a 4-wire RTD application where the RTD
transducer is interfaced directly to the AD7711. In the 4-wire
configuration, there are no errors associated with lead resistances
because no current flows in the measurement leads connected to
AIN1(+) and AIN1(–). One of the RTD current sources is used
to provide the excitation current for the RTD. A common nominal
resistance value for the RTD is 100
W and, therefore, the RTD
will generate a 20 mV signal that can be handled directly by the
analog input of the AD7711. In the circuit shown, the second
RTD excitation current is used to generate the reference voltage
for the AD7711. This reference voltage is developed across RREF
and applied to the differential reference inputs. For the nominal
reference voltage of 2.5 V, RREF is 12.5 k
W. This scheme ensures
that the analog input voltage span remains ratiometric to the
reference voltage. Any errors in the analog input voltage due to
the temperature drift of the RTD current source is compensated
for by the variation in the reference voltage. The typical matching
between the RTD current sources is less than 3 ppm/
∞C.
INTERNAL
CIRCUITRY
200 A
PGA
AD7711
A = 1–128
RTD2
REF IN(+)
REF IN(–)
RTD1
AIN1(+)
AIN1(–)
AGND
RREF
RTD
5V
AVDD
DVDD
VSS
DGND
Figure 19. 4-Wire RTD Application with the AD7711
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