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参数资料
| 型号： | AD7711AQ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT RTD I SOURCE 24CDIP |
| 标准包装： | 15 |
| 位数： | 24 |
| 采样率（每秒）： | 1.03k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 52.5mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 80°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 24-CDIP（0.300"，7.62mm） |
| 供应商设备封装： | 24-CDIP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，单极；1 个单端，双极；1 个差分，单极；1 个差分，双极 |
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REV. G
–16–
AD7711
IN(+) pin. This REF OUT pin is a single-ended output, refer-
enced to AGND, which is capable of providing up to 1 mA to
an external load. In applications where REF OUT is connected
directly to REF IN(+), REF IN(–) should be tied to AGND to
provide the nominal 2.5 V reference for the AD7711.
The reference inputs of the AD7711, REF IN(+) and REF IN(–),
provide a differential reference input capability. The common-
mode range for these differential inputs is from VSS to AVDD.
The nominal differential voltage, VREF (REF IN(+) – REF IN(–)),
is 2.5 V for specified operation, but the reference voltage can go
to 5 V with no degradation in performance if the absolute value
of REF IN(+) and REF IN(–) does not exceed its AVDD and
VSS limits and the VBIAS input voltage range limits are obeyed.
The part is also functional with VREF voltages down to 1 V but with
degraded performance because the output noise will, in terms
of LSB size, be larger. REF IN(+) must always be greater than
REF IN(–) for correct operation of the AD7711.
Both reference inputs provide a high impedance, dynamic load
similar to the analog inputs. The maximum dc input leakage
current is 10 pA (
±1 nA over temperature), and source resis-
tance may result in gain errors on the part. The reference inputs
look like the analog input (see Figure 7). In this case, RINT is
5 k
W typ and CINT varies with gain. The input sample rate is
fCLK IN/256 and does not vary with gain. For gains of 1 to 8, CINT
is 20 pF; for a gain of 16, it is 10 pF; for a gain of 32, it is 5 pF; for
a gain of 64, it is 2.5 pF; and for a gain of 128, it is 1.25 pF.
The digital filter of the AD7711 removes noise from the refer-
ence input just as it does with the analog input, and the same
limitations apply regarding lack of noise rejection at integer
multiples of the sampling frequency. The output noise perfor-
mance outlined in Tables I and II assumes a clean reference. If
the reference noise in the bandwidth of interest is excessive, it
can degrade the performance of the AD7711. Using the on-chip
reference as the reference source for the part (connecting
REF OUT to REF IN) results in degraded output noise perfor-
mance from the AD7711 for portions of the noise table that are
dominated by the device noise. The on-chip reference noise
effect is eliminated in ratiometric applications where the refer-
ence is used to provide the excitation voltage for the analog
front end. The connection shown in Figure 8 is recommended
when using the on-chip reference. Recommended reference
voltage sources for the AD7711 include the AD580 and AD680
2.5 V references.
AD7711
REF OUT
REF IN(+)
REF IN(–)
Figure 8. REF OUT/REF IN Connection
VBIAS Input
The VBIAS input determines at what voltage the internal analog
circuitry is biased. It essentially provides the return path for
analog currents flowing in the modulator and, as such, it should
be driven from a low impedance point to minimize errors.
For maximum internal headroom, the VBIAS voltage should be
set halfway between AVDD and VSS. The difference between
AVDD and (VBIAS + 0.85
VREF) determines the amount of
headroom the circuit has at the upper end, while the difference
between VSS and (VBIAS – 0.85
VREF) determines the amount
of headroom the circuit has at the lower end. When choosing a
VBIAS voltage, ensure that it stays within prescribed limits. For
single 5 V operation, the selected VBIAS voltage must ensure that
VBIAS
± 0.85 VREF does not exceed AVDD or VSS or that the
VBIAS voltage itself is greater than VSS + 2.1 V and less than
AVDD – 2.1 V. For single 10 V operation or dual
±5 V opera-
tion, the selected VBIAS voltage must ensure that VBIAS
0.85
VREF does not exceed AVDD or VSS or that the VBIAS voltage
itself is greater than VSS + 3 V or less than AVDD – 3 V. For
example, with AVDD = 4.75 V, VSS = 0 V, and VREF = 2.5 V, the
allowable range for the VBIAS voltage is 2.125 V to 2.625 V. With
AVDD = 9.5 V, VSS = 0 V, and VREF = 5 V, the range for VBIAS
is 4.25 V to 5.25 V. With AVDD = +4.75 V, VSS = –4.75 V,
and VREF = +2.5 V, the VBIAS range is –2.625 V to +2.625 V.
The VBIAS voltage does have an effect on the AVDD power sup-
ply rejection performance of the AD7711. If the VBIAS voltage
tracks the AVDD supply, it improves the power supply rejection
from the AVDD supply line from 80 dB to 95 dB. Using an
external Zener diode connected between the AVDD line and
VBIAS as the source for the VBIAS voltage gives the improvement
in AVDD power supply rejection performance.
USING THE AD7711
SYSTEM DESIGN CONSIDERATIONS
The AD7711 operates differently from successive approxima-
tion ADCs or integrating ADCs. Because it samples the signal
continuously, like a tracking ADC, there is no need for a start
convert command. The output register is updated at a rate
determined by the first notch of the filter, and the output can
be read at any time, either synchronously or asynchronously.
Clocking
The AD7711 requires a master clock input, which may be an
external TTL/CMOS compatible clock signal applied to the
MCLK IN pin with the MCLK OUT pin left unconnected.
Alternatively, a crystal of the correct frequency can be connected
between MCLK IN and MCLK OUT, in which case the clock
circuit will function as a crystal-controlled oscillator. For lower
clock frequencies, a ceramic resonator may be used instead of
the crystal. For these lower frequency oscillators, external
capacitors may be required on either the ceramic resonator or
on the crystal.
The input sampling frequency, the modulator sampling frequency,
the –3 dB frequency, the output update rate, and the calibration
time are all directly related to the master clock frequency,
fCLK IN. Reducing the master clock frequency by a factor of 2 will
halve the above frequencies and update rate and will double the
calibration time.
The current drawn from the DVDD power supply is also directly
related to fCLK IN. Reducing fCLK IN by a factor of 2 will halve the
DVDD current but will not affect the current drawn from the
AVDD power supply.
System Synchronization
If multiple AD7711s are operated from a common master clock,
they can be synchronized to update their output registers simul-
taneously. A falling edge on the
SYNC input resets the filter and
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