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| 型号： | AD7731BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24TSSOP |
| 标准包装： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 6.4k |
| 数据接口： | DSP，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 125mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 3 个差分，单极；3 个差分，双极；5 个伪差分，单极；5 个伪差分，双极 |
| 产品目录页面： | 779 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731 |
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AD7731
–18–
REV. 0
Bit
Location
Mnemonic
Description
MR3
BO
Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout
currents connect to the selected analog input pair, one source current to the AIN(+) input
and one sink current to the AIN(–) input. A 0 in this bit turns off the on-chip burnout
currents.
MR2–MR0
CH2–CH0
Channel Select. These three bits select a channel either for conversion or for access to cali-
bration coefficients as outlined in Table XIII. There are three pairs of calibration registers on
the part. In fully differential mode, the part has three input channels so each channel has its
own pair of calibration registers. In pseudo-differential mode, the AD7731 has five input
channels with some of the input channel combinations sharing calibration registers. With
CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself.
This can be used as a test method to evaluate the noise performance of the part with no ex-
ternal noise sources. In this mode, the AIN6 input should be connected to an external volt-
age within the allowable common-mode range for the part. The power-on/default status of
these bits is 1, 0, 0.
Table XIII. Channel Selection
CH2
CH1
CH0 AIN(+) AIN(–) Type
Calibration Register Pair
0
AIN1
AIN6
Pseudo Differential
Register Pair 0
0
1
AIN2
AIN6
Pseudo Differential
Register Pair 1
0
1
0
AIN3
AIN6
Pseudo Differential
Register Pair 2
0
1
AIN4
AIN6
Pseudo Differential
Register Pair 2
1
0
AIN1
AIN2
Fully Differential
Register Pair 0
1
0
1
AIN3
AIN4
Fully Differential
Register Pair 1
1
0
AIN5
AIN6
Fully Differential
Register Pair 2
1
AIN6
Test Mode
Register Pair 2
Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 2002 Hex
The Filter Register is a 16-bit register from which data can either be read or to which data can be written. This register determines
the amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode. Table XIV
outlines the bit designations for the Filter Register. FR0 through FR15 indicate the bit location, FR denoting the bits are in the Filter
Register. FR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers
on the part.
Table XIV. Filter Register
5
1
R
F4
1
R
F3
1
R
F2
1
R
F1
1
R
F0
1
R
F9
R
F8
R
F
)
0
(
1
F
S)
0
(
0
1
F
S)
1
(
9
F
S)
0
(
8
F
S)
0
(
7
F
S)
0
(
6
F
S)
0
(
5
F
S)
0
(
4
F
S
7
R
F6
R
F5
R
F4
R
F3
R
F2
R
F1
R
F0
R
F
)
0
(
3
F
S)
0
(
2
F
S)
0
(
1
F
S)
0
(
0
F
S)
0
(
O
R
E
Z)
0
(
P
H
C)
1
(
P
I
K
S)
0
(
T
S
A
F
Bit
Location
Mnemonic
Description
FR15–FR4
SF11–SF0
Sinc
3 Filter Selection Bits. The AD7731 contains two filters, a Sinc3 filter and an FIR filter.
The 12 bits programmed to SF11 through SF0 sets the amount of averaging which the Sinc
3
filter performs. As a result, the number programmed to these 12 bits affects the –3 dB fre-
quency and output update rate from the part (see Filter Architecture section). The allowable
range for SF words depends on whether the part is operated with CHP on or off and SKIP
on or off. Table XV outlines the SF ranges for different setups.
REV. A
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