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| 型号： | AD7731BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24TSSOP |
| 标准包装： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 6.4k |
| 数据接口： | DSP，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 125mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 3 个差分，单极；3 个差分，双极；5 个伪差分，单极；5 个伪差分，双极 |
| 产品目录页面： | 779 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731 |
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AD7731
–21–
REV. 0
CALIBRATION OPERATION SUMMARY
The AD7731 contains a number of calibration options as outlined previously. Table XVI summarizes the calibration types, the op-
erations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to
monitor the hardware
RDY pin using either interrupt-driven or polling routines. The second method is to do a software poll of the
RDY bit in the Status Register. This can be achieved by setting up the part for continuous reads of the Status Register once a calibra-
tion has been initiated. The
RDY pin and RDY bit go high on initiating a calibration and return low at the end of the calibration
routine. At this time, the MD2, MD1, MD0 bits of the Mode Register have returned to 0, 0, 0. The FAST and SKIP bits are treated
as 0 for the calibration sequence so the full filter is always used for the calibration routines. See Calibration section for full details.
Table XVI. Calibration Operations
MD2, MD1, Duration to
RDY Duration to RDY
Calibration Type
MD0
Low (CHP = 1)
Low (CHP = 0)
Calibration Sequence
Internal Zero-Scale
1, 0, 0
22
× 1/Output Rate 24 × 1/Output Rate Calibration on internal shorted input with PGA set
for selected input range. The Offset Calibration
Register for the selected channel is updated at the
end of this calibration sequence. For full self-cali-
bration, this calibration should be preceded by an
Internal Full-Scale calibration. For applications
which require an Internal Zero-Scale and System
Full Scale calibration, this Internal Zero-Scale
calibration should be performed first.
Internal Full-Scale
1, 0, 1
44
× 1/Output Rate 48 × 1/Output Rate Calibration on internally-generated input full-scale
with PGA set for selected input range. The Gain
Calibration Register for the selected channel is
updated at the end of this calibration sequence. It is
recommended that internal full-scale calibrations
are performed on the operating input range except
for the 20 mV and 40 mV input ranges where opti-
mum results are achieved by calibrating on the
80 mV range. This calibration should be followed
by either an Internal Zero-Scale or System Zero-
Scale calibration. This calibration should be fol-
lowed by either an Internal Zero-Scale or System
Zero-Scale calibration. This zero-scale calibration
should be performed at the operating input range.
System Zero-Scale
1, 1, 0
22
× 1/Output Rate 24 × 1/Output Rate Calibration on externally-applied input voltage with
PGA set for selected input range. The input applied
is assumed to be the zero-scale of the system. For
full system calibration, this System Zero-Scale
calibration should be performed first. For applica-
tions which require a System Zero-Scale and Inter-
nal Full Scale calibration, this calibration should be
preceded by the Internal Full-Scale calibration. The
Offset Calibration Register for the selected channel
is updated at the end of this calibration sequence.
System Full-Scale
1, 1, 1
22
× 1/Output Rate 24 × 1/Output Rate Calibration on externally-applied input voltage with
PGA set for selected input range. The input applied
is assumed to be the full-scale of the system. This
calibration should be preceded by a System Zero-
Scale or Internal Zero-Scale calibration. The Gain
Calibration Register for the selected channel is
updated at the end of this calibration sequence.
REV. A
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