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| 型号： | AD7731BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 44/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24TSSOP |
| 标准包装： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 6.4k |
| 数据接口： | DSP，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 125mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 3 个差分，单极；3 个差分，双极；5 个伪差分，单极；5 个伪差分，双极 |
| 产品目录页面： | 779 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731 |
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AD7731
–9–
REV. 0
PIN FUNCTION DESCRIPTIONS (Continued)
Pin
No.
Mnemonic
Function
20
RDY
Logic output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a
logic low on this output indicates that a new output word is available from the AD7731 data register. The
RDY pin will return high upon completion of a read operation of a full output word. If no data read has
taken place after an output update, the
RDY line will return high prior to the next output update, remain
high while the update is taking place and return low again. This gives an indication of when a read operation
should not be initiated to avoid initiating a read from the data register as it is being updated. In calibration
mode,
RDY goes high when calibration is initiated and returns low to indicate that calibration is complete. A
number of different events on the AD7731 set the
RDY high and these are outlined in Table XVII.
21
DOUT
Serial Data Output with serial data being read from the output shift register on the part. This output shift
register can contain information from the calibration registers, mode register, status register, filter register or
data register depending on the register selection bits of the Communications Register.
22
DIN
Serial Data Input with serial data being written to the input shift register on the part. Data from this input
shift register is transferred to the calibration registers, mode register, communications register or filter regis-
ter depending on the register selection bits of the Communications Register.
23
DVDD
Digital Supply Voltage, +3 V or +5 V nominal.
24
DGND
Ground reference point for digital circuitry.
TERMINOLOGY
INTEGRAL NONLINEARITY
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi-
tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111). The
error is expressed as a percentage of full scale.
POSITIVE FULL-SCALE ERROR
Positive Full-Scale Error is the deviation of the last code transi-
tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage
(AIN(–) + VREF/GAIN – 3/2 LSBs). It applies to both unipolar
and bipolar analog input ranges.
UNIPOLAR OFFSET ERROR
Unipolar Offset Error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-
ating in the unipolar mode.
BIPOLAR ZERO ERROR
This is the deviation of the midscale transition (0111 ...111
to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) –
0.5 LSB) when operating in the bipolar mode.
GAIN ERROR
This is a measure of the span error of the ADC. It is a measure
of the difference between the measured and the ideal span be-
tween any two points in the transfer function. The two points
used to calculate the gain error are positive full scale and nega-
tive full scale.
BIPOLAR NEGATIVE FULL-SCALE ERROR
This is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5 LSB) when operat-
ing in the bipolar mode. Negative full-scale error is a summation
of zero error and gain error.
POSITIVE FULL-SCALE OVERRANGE
Positive Full-Scale Overrange is the amount of overhead avail-
able to handle input voltages on AIN(+) input greater than
AIN(–) + VREF/GAIN (for example, noise peaks or excess volt-
ages due to system gain errors in system calibration routines)
without introducing errors due to overloading the analog modu-
lator or overflowing the digital filter.
NEGATIVE FULL-SCALE OVERRANGE
This is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) – VREF/GAIN without overloading the
analog modulator or overflowing the digital filter.
OFFSET CALIBRATION RANGE
In the system calibration modes, the AD7731 calibrates its
offset with respect to the analog input. The Offset Calibration
Range specification defines the range of voltages the AD7731
can accept and still accurately calibrate offset.
FULL-SCALE CALIBRATION RANGE
This is the range of voltages that the AD7731 can accept in the
system calibration mode and still accurately calibrate full scale.
INPUT SPAN
In system calibration schemes, two voltages applied in sequence
to the AD7731’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full scale that the AD7731 can
accept and still accurately calibrate gain.
REV. A
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