参数资料
| 型号： | AD7762BSVZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 625KSPS 64TQFP |
| 标准包装： | 1,500 |
| 位数： | 24 |
| 采样率（每秒）： | 625k |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 958mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-TQFP-EP（10x10） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
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AD7762
Data Sheet
Rev. A | Page 8 of 28
Pin No.
Mnemonic
Description
10
VREF+
Reference Input. The input range of this pin is determined by the reference buffer supply voltage
8
DECAPA
Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND1.
30
DECAPB
Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3.
17
RBIAS
Bias Current Setting Pin. A resistor must be inserted between this pin and AGND1. For more details, see
the Bias Resistor Selection section.
45 to 52,
54 to 61
DB15 to DB8
DB7 to DB0
16-Bit Bidirectional Data Bus. These are three-state pins that are controlled by the CS pin and the RD/WR
pin. The operating voltage for these pins is determined by the VDRIVE voltage. See the AD7762 Interface
section for more details.
37
RESET
A falling edge on this pin resets all internal digital circuitry and powers down the part. Holding this pin
low keeps the AD7762 in a reset state.
3
MCLK
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends
on the frequency of this clock. See the section Clocking the AD7762 for more details.
2
MCLKGND
Master Clock Ground Sensing Pin.
36
SYNC
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to
synchronize multiple devices in a system.
39
RD/WR
Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and
from the AD7762. If this pin is low when CS is low, a read takes place. If this pin is high and CS is low, a
write occurs. See the AD7762 Interface section for more details.
38
DRDY
Data Ready Output. Each time that new conversion data is available, an active low pulse, ICLK period
wide, is produced on this pin. See the AD7762 Interface section for more details.
40
CS
Chip Select Input. Used in conjunction with the RD/WR pin to read and write data to and from the
EPAD
Exposed pad. Connect the exposed pad to AGNDx with six to eight vias.
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| AD7763BSVZ | 功能描述:IC ADC 24BIT SRL 625KSPS 64TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD7763BSVZ-REEL | 功能描述:IC ADC 24BIT S/D 625KSPS 64-TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
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