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| 型号： | AD7853LARS |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/34页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL 200KSPS 24-SSOP |
| 标准包装： | 59 |
| 位数： | 12 |
| 采样率（每秒）： | 100k |
| 数据接口： | 8051，QSPI?，串行，SPI? µP |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 33mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个伪差分，单极；1 个伪差分，双极 |
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REV. B
–4–
AD7853/AD7853L
TIMING SPECIFICATIONS
1
Limit at TMIN, TMAX
(A, B Versions)
Parameter
5 V
3 V
Units
Description
fCLKIN
2
500
kHz min
Master Clock Frequency
4
MHz max
1.8
MHz max
L Version, 0
°C to +70°C, B Grade Only
1
MHz max
L Version, –40
°C to +85°C
fSCLK
3
4
MHz max
Interface Modes 1, 2, 3 (External Serial Clock)
fCLKIN
MHz max
Interface Modes 4, 5 (Internal Serial Clock)
t1
4
100
ns min
CONVST Pulsewidth
t2
50
90
ns max
CONVST
↓ to BUSY↑ Propagation Delay
tCONVERT
4.6
s max
Conversion Time = 18 tCLKIN
10 (18)
s max
L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 tCLKIN
t3
–0.4 tSCLK
ns min
SYNC
↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
0.4 tSCLK
ns min/max
SYNC
↓ to SCLK↓ Setup Time (Continuous SCLK Input)
t4
0.6 tSCLK
ns min
SYNC
↓ to SCLK↓ Setup Time. Interface Mode 4 Only
t5
5
50
90
ns max
Delay from
SYNC
↓ until DOUT 3-State Disabled
t5A
5
50
90
ns max
Delay from
SYNC
↓ until DIN 3-State Disabled
t6
5
75
115
ns max
Data Access Time After SCLK
↓
t7
40
60
ns min
Data Setup Time Prior to SCLK
↑
t8
20
30
ns min
Data Valid to SCLK Hold Time
t9
6
0.4 tSCLK
ns min
SCLK High Pulsewidth (Interface Modes 4 and 5)
t10
6
0.4 tSCLK
ns min
SCLK Low Pulsewidth (Interface Modes 4 and 5)
t11
30
50
ns min
SCLK
↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
30/0.4 tSCLK
50/0.4 tSCLK ns min/max
(Continuous SCLK) Does Not Apply to Interface Mode 3
t11A
50
ns max
SCLK
↑ to SYNC↑ Hold Time
t12
7
50
ns max
Delay from
SYNC
↑ until DOUT 3-State Enabled
t13
90
130
ns max
Delay from SCLK
↑ to DIN Being Configured as Output
t14
8
50
90
ns max
Delay from SCLK
↑ to DIN Being Configured as Input
t15
2.5 tCLKIN
ns max
CAL
↑ to BUSY↑ Delay
t16
2.5 tCLKIN
ns max
CONVST
↓ to BUSY↑ Delay in Calibration Sequence
tCAL
9
31.25
ms typ
Full Self-Calibration Time, Master Clock Dependent
(125013 tCLKIN)
tCAL1
9
27.78
ms typ
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111114 tCLKIN)
tCAL2
9
3.47
ms typ
System Offset Calibration Time, Master Clock Dependent
(13899 tCLKIN)
NOTES
Descriptions that refer to SCLK
↑ (rising) or SCLK↓ (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of
SCLK will apply.
1Sample tested at +25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.
2Mark/Space ratio for the master clock input is 40/60 to 60/40.
3For Interface Modes 1, 2, 3 the SCLK max frequency will be 4 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f
CLKIN.
4The
CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply (see Power-
Down section).
5Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t
SCLK = 0.5 tCLKIN.
7t
12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus relin-
quish time of the part and is independent of the bus loading.
8t
14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part
in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will
not occur.
9The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8/1 MHz master clock.
Specifications subject to change without notice.
(AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7853 and 1.8/1 MHz for AD7853L; TA = TMIN to
TMAX, unless otherwise noted)
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| AD7853LARS-REEL | 功能描述:IC ADC 12BIT SRL 200KSPS 24-SSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
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