参数资料
型号: AD7856KRZ
厂商: Analog Devices Inc
文件页数: 18/32页
文件大小: 0K
描述: IC ADC 14BIT 8CHAN 5V 24SOIC
标准包装: 31
位数: 14
采样率(每秒): 285k
数据接口: 8051,QSPI?,串行,SPI? µP
转换器数目: 2
功率耗散(最大): 89.25mW
电压电源: 模拟和数字
工作温度: 0°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 管件
输入数目和类型: 8 个单端,单极;4 个伪差分,单极
AD7856
–25–
REV. A
Mode 2 (3-Wire SPI/QSPI Interface Mode)
This is the DEFAULT INTERFACE MODE.
In Figure 33 below we have the timing diagram for interface
Mode 2, which is the SPI/QSPI interface mode. Here the
SYNC
input is active low and may be pulsed or permanently tied low.
If
SYNC is permanently low, 16 clock pulses must be applied to
the SCLK pin for the part to operate correctly otherwise, with a
pulsed
SYNC input, a continuous SCLK may be applied pro-
vided
SYNC is low for only 16 SCLK cycles. In Figure 33 the
t3 = –0.4tSCLK MIN (NONCONTINUOUS SCLK) –/+0.4tSCLK ns MIN/MAX (CONTINUOUS SCLK),
t6 = 45/75ns MAX (A/K), t7 = 30/40ns MIN (A/K), t8 = 20ns MIN,
t11 = 30ns MIN (NONCONTINUOUS SCLK), 30/0.4tSCLK ns MIN/MAX (CONTINUOUS SCLK)
t11
t12
16
6
5
4
3
2
1
t10
t8
t6
t9
t8
t6
t3
t5
THREE-
STATE
DB0
DB10
DB11
DB12
DB13
DB14
DB15
DB14
DB13
DB12
DB11
DB10
DB0
SYNC (I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
POLARITY PIN LOGIC HIGH
t7
THREE-
STATE
Figure 33. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input
DOUT Output and
SYNC Input
SYNC going low disables the three-state on the DOUT pin. The
first falling edge of the SCLK after the
SYNC going low clocks
out the first leading zero on the DOUT pin. The DOUT pin is
three-stated again a time, t12, after the SYNC goes high. With
the DIN pin the data input has to be set up a time, t7, before the
SCLK rising edge as the part samples the input data on the
SCLK rising edge in this case. If resetting the interface is re-
quired, the
SYNC must be taken high and then low.
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