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参数资料
| 型号： | AD7866ARUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 2CHAN DUAL 20TSSOP |
| 标准包装： | 2,500 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 24mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极 |
| 配用： | EVAL-AD7866CBZ-ND - BOARD EVALUATION AD7866 |
REV. A
–18–
AD7866
POWER VS. THROUGHPUT RATE
When the AD7866 is in partial power-down mode and not
converting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 21 shows that as the through-
put rate is reduced, the part remains in its partial power-down
state longer, and the average power consumption over time
drops accordingly.
THROUGHPUT – kSPS
0.01
0
POWER
–
mW
50
100
VDD = 5V
SCLK = 20MHz
150
200
250
300
350
0.1
1
10
100
VDD = 3V
SCLK = 20MHz
Figure 21. Power vs. Throughput for Partial Power-Down
For example, if the AD7866 is operated in a continuous sampling
mode with a throughput rate of 100 kSPS and an SCLK of
20 MHz (VDD = 5 V), and the device is placed in partial power-
down mode between conversions, the power consumption is
calculated as follows. The maximum power dissipation during
normal operation is 24 mW (VDD = 5 V). If the power-up time
allowed from partial power-down is one dummy cycle, i.e., 1
s,
(assuming use of an external reference) and the remaining
conversion time is another cycle, i.e., 1
s, then the AD7866
can be said to dissipate 24 mW for 2
s during each conversion
cycle. For the remainder of the conversion cycle, 8
s, the part
remains in partial power-down mode. The AD7866 can be said to
dissipate 2.8 mW for the remaining 8
s of the conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10
s and the
average power dissipated during each cycle is (2/10)
(24 mW) +
(8/10)
(2.8 mW) = 7.04 mW. If VDD = 3 V, SCLK = 20 MHz,
and the device is again in partial power-down mode between
conversions, the power dissipated during normal operation is
11.4 mW. The AD7866 can be said to dissipate 11.4 mW for 2
s
during each conversion cycle and 1.68 mW for the remaining 8
s
when the part is in partial power-down. With a throughput rate of
100 kSPS, the average power dissipated during each conversion
cycle is (2/10)
(11.4 mW) + (8/10)
(1.68 mW) = 3.624 mW.
Figure 21 shows the maximum power versus throughput rate
when using the partial power-down mode between conversions
with both 5 V and 3 V supplies for the AD7866.
SERIAL INTERFACE
Figure 22 shows the detailed timing diagram for serial interfacing
to the AD7866. The serial clock provides the conversion clock
and controls the transfer of information from the AD7866
during conversion.
The
CS signal initiates the data transfer and conversion process.
The falling edge of
CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. Once 13 SCLK falling
edges have elapsed, the track-and-hold will go back into track
on the next SCLK rising edge, as shown in Figure 22 at point
B. On the rising edge of
CS, the conversion will be terminated
and DOUTA and DOUTB will go back into three-state. If CS is
not brought high but is instead held low for a further 16 SCLK
cycles on DOUTA, the data from conversion B will be output on
CS
SCLK
DOUTA
DOUTB
t2
12
3
4
5
13
14
15
16
t3
t4
t7
t5
t8
tQUIET
0
RANGE
A0
A/B
DB11
DB2
DB1
DB0
THREE-
STATE
1 LEADING ZERO
3 STATUS BITS
DB10
THREE-
STATE
t6
B
Figure 22. Serial Interface Timing Diagram
CS
SCLK
DOUTA
t2
t4
t7
t5
0
RANGE
DB11A
A0/
A0
ZERO
DB1A
DB0A
ZERO
RANGE
A0/
A0
ONE
DB11B
DB1B
DB0B
THREE-
STATE
t6
t9
1 LEADING ZERO
3 STATUS BITS
1 LEADING ZERO
3 STATUS BITS
THREE-
STATE
t3
1
2
3
4
5
14
15
16
17
32
Figure 23. Reading Data from Both ADCs on One DOUT Line
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