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参数资料
| 型号： | AD7898ARZ-3 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL HS 5V 8SOIC |
| 标准包装： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 220k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 22.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，双极 |
–3–
REV. A
AD7898
Parameter
Limit at TMIN, TMAX
Unit
Description
Mode 0 Operation
t1
40
ns min
CONVST Pulse Width
t2
26
2
ns min
SCLK High Pulse Width, VDRIVE = 5 V
± 5%
t3
26
2
ns min
SCLK Low Pulse Width, VDRIVE = 5 V
± 5%
30
2
ns min
SCLK High Pulse Width VDRIVE = 2.7 V to 3.6 V
30
2
ns min
SCLK Low Pulse Width VDRIVE = 2.7 V to 3.6 V
t4
60
3
ns max
Data Access Time after Falling Edge of SCLK, VDRIVE = 5 V
± 5%
t4
70
3
ns max
Data Access Time after Falling Edge of SCLK, VDRIVE = 2.7 V to 3.6 V
t5
20
ns min
Data Hold Time after Falling Edge of SCLK
t6
50
4
ns max
Bus Relinquish Time after Falling Edge of SCLK
tCONVERT
3.3
s
Mode 1 Operation
fSCLK
5
1kHz min
3.7
MHz max
tCONVERT
16
× t
SCLK
tSCLK = 1/fSCLK
4.33
s max
fSCLK = 3.7 MHz
tQUIET
100
ns min
Minimum Quiet Time Required between Conversions
t2
70
ns min
CS to SCLK Setup Time
t3
3
40
ns max
Delay from
CS Until SDATA Three-State Disabled
t4
3
80
ns max
Data Access Time after SCLK Falling Edge
t5
108
ns min
SCLK High Pulse Width
t6
108
ns min
SCLK Low Pulse Width
t7
60
ns min
SCLK to Data Valid Hold Time
t8
4
20
ns min
SCLK Falling Edge to SDATA High Impedance
60
ns max
SCLK Falling Edge to SDATA High Impedance
tPOWER-UP
4.33
s max
Power-Up Time from Power-Down Mode
NOTES
1Sample tested at 25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V.
2The SCLK maximum frequency is 15 MHz for Mode 0 operation for 220 kSPS throughput with V
DRIVE = 5 V
± 5%, SCLK = 13 MHz with V
DRIVE = 2.7 V to 3.6 V.
The mark/space ratio for SCLK is specified for at least 40% high time (with corresponding 60% low time) or 40% low time (with corresponding 60% high time). As
the SCLK frequency is reduced, the mark/space ratio may vary, provided limits are not exceeded. Care must be taken when interfacing to account for the data access
time, t4, and the set-up time required for the users processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with.
See Serial Interface section.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4t
6 and t8 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number i s then extrapo-
lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 6 and t8, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
5Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1
(VDD = 4.75 V to 5.25 V; VDRIVE = 2.7 V to 5.25 V; REF IN = 2.5 V; TA = TMIN to TMAX, unless otherwise
noted.)
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