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| 型号： | AD7952BSTZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT DIFF 1MSPS 48-LQFP |
| 标准包装： | 2,000 |
| 系列： | PulSAR® |
| 位数： | 14 |
| 采样率（每秒）： | 1M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 260mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
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AD7952
Data Sheet
Rev. A | Page 4 of 32
Parameter
Conditions/Comments
Min
Typ
Max
Unit
INTERNAL REFERENCE
PDREF = PDBUF = low
Output Voltage
REF @ 25°C
4.965
5.000
5.035
V
Temperature Drift
–40°C to +85°C
±3
ppm/°C
Line Regulation
AVDD = 5 V ± 5%
±15
ppm/V
Long-Term Drift
1000 hours
50
ppm
Turn-On Settling Time
CREF = 22 μF
10
ms
REFERENCE BUFFER
PDREF = high
REFBUFIN Input Voltage Range
2.4
2.5
2.6
V
EXTERNAL REFERENCE
PDREF = PDBUF = high
Voltage Range
REF
4.75
5
AVDD + 0.1
V
Current Drain
1 MSPS throughput
200
μA
TEMPERATURE PIN
Voltage Output
@ 25°C
311
mV
Temperature Sensitivity
1
mV/°C
Output Resistance
4.33
kΩ
DIGITAL INPUTS
Logic Levels
VIL
0.3
+0.6
V
VIH
2.1
OVDD + 0.3
V
IIL
1
+1
μA
IIH
1
+1
μA
DIGITAL OUTPUTS
Data Format
Parallel or serial 14-bit
Pipeline Delay5
VOL
ISINK = 500 μA
0.4
V
VOH
ISOURCE = 500 μA
OVDD 0.6
V
POWER SUPPLIES
Specified Performance
AVDD
4.756
5
5.25
V
DVDD
4.75
5
5.25
V
OVDD
2.7
5.25
V
VCC
7
15
15.75
V
VEE
15.75
15
0
V
Operating Current7, 8
@ 1 MSPS throughput
AVDD
With Internal Reference
20
mA
With Internal Reference Disabled
18.5
mA
DVDD
7
mA
OVDD
0.5
mA
VCC
VCC = 15 V, with internal reference buffer
4
mA
VCC = 15 V
3
mA
VEE
VEE = 15 V
2
mA
Power Dissipation
@ 1 MSPS throughput
With Internal Reference
PDREF = PDBUF = low
235
260
mW
With Internal Reference Disabled
PDREF = PDBUF = high
215
240
mW
In Power-Down Mode9
PD = high
10
μW
TEMPERATURE RANGE10
Specified Performance
TMIN to TMAX
40
+85
°C
1 With VIN = unipolar 5 V or unipolar 10 V ranges, the input current is typically 70 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section.
2 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.
3 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.
4 All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5 Conversion results are available immediately after completed conversion.
6 4.75 V or VREF 0.1 V, whichever is larger.
7 Tested in parallel reading mode.
8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.
9 With all digital inputs forced to OVDD.
10 Consult sales for extended temperature range.
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