参数资料
| 型号： | AD8195ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC BUFF HDMI/DVI W/EQUAL 40LFCSP |
| 标准包装： | 1 |
| 功能： | 开关 |
| 电路： | 1 x 1:1 |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
Data Sheet
AD8195
Rev. B | Page 17 of 20
TMDS Signals
In the HDMI/DVI standard, four differential pairs carry the
TMDS signals. In DVI, three of these pairs are dedicated to
carrying RGB video and sync data. For HDMI, audio data is
also interleaved with the video data; the DVI standard does not
incorporate audio information. The fourth high speed differential
pair is used for the AV data-word clock and runs at one-tenth
the speed of the TMDS data channels.
The four high speed channels of the AD8195 are identical.
No concession was made to lower the bandwidth of the fourth
channel for the pixel clock, so any channel can be used for any
TMDS signal. The user chooses which signal is routed over
which channel. Additionally, the TMDS channels are symmetric;
therefore, the p and n of a given differential pair are interchange-
able, provided the inversion is consistent across all inputs and
outputs of the AD8195. However, the routing between inputs
and outputs through the AD8195 is fixed. For example, Input
Channel 0 is always buffered to Output Channel 0, and so forth.
The AD8195 buffers the TMDS signals, and the input traces can
be considered electrically independent of the output traces. In
most applications, the quality of the signal on the input TMDS
traces is more sensitive to the PCB layout. Regardless of the data
being carried on a specific TMDS channel, or whether the TMDS
line is at the input or the output of the AD8195, all four high
speed signals should be routed on a PCB in accordance with the
same RF layout guidelines.
Layout for the TMDS Signals
The TMDS differential pairs can be either microstrip traces,
routed on the outer layer of a board, or stripline traces, routed
on an internal layer of the board. If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack-up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 . The
characteristic impedance of a differential pair is a function of
several variables, including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PCB binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path; therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. In addition, to prevent
unwanted signal coupling and interference, route the TMDS
signals away from other signals and noise sources on the PCB.
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). The p and n of a given differential pair should
always be routed together in order to establish the required
100 differential impedance. Enough space should be left
between the differential pairs of a given group so that the n of
one pair does not couple to the p of another pair. For example, one
technique is to make the interpair distance 4 to 10 times wider
than the intrapair spacing.
Any group of four TMDS channels (input or output) should have
closely matched trace lengths to minimize interpair skew. Severe
interpair skew can cause the data on the four different channels
of a group to arrive out of alignment with one another. A good
practice is to match the trace lengths for a given group of four
channels to within 0.05 inches on FR4 material.
The length of the TMDS traces should be minimized to reduce
overall signal degradation. Commonly used PCB material, such
as FR4, is lossy at high frequencies, so long traces on the circuit
board increase signal attenuation, resulting in decreased signal
swing and increased jitter through intersymbol interference (ISI).
Controlling the Characteristic Impedance of a TMDS
Differential Pair
The characteristic impedance of a differential pair depends on a
number of variables, including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask.
There are many combinations that can produce the correct
characteristic impedance. It is generally required to work with
the PCB fabricator to obtain a set of parameters to produce the
desired results.
One consideration is how to guarantee a differential pair with a
differential impedance of 100 over the entire length of the trace.
One technique is to change the width of the traces in a differential
pair based on how closely one trace is coupled to the other. When
the two traces of a differential pair are close and strongly coupled,
they should have a width that produces a 100 differential
impedance. When the traces split apart to go into a connector,
for example, and are no longer so strongly coupled, the width of
the traces should be increased to yield a differential impedance of
100 in the new configuration.
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