参数资料
型号: AD9222ABCPZ-65
厂商: Analog Devices Inc
文件页数: 45/60页
文件大小: 0K
描述: IC ADC 12BIT SRL 65MSPS 64LFCSP
标准包装: 1
位数: 12
采样率(每秒): 65M
数据接口: 串行,SPI?
转换器数目: 8
功率耗散(最大): 950.5mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 托盘
输入数目和类型: 16 个单端,单极;8 个差分,单极
Data Sheet
AD9222
Rev. F | Page 5 of 60
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 0.5 dBFS, unless otherwise noted.
Table 3.
AD9222-40
AD9222-50
AD9222-65
Parameter1
Temp
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Full
250
mV p-p
Input Common-Mode Voltage
Full
1.2
V
Input Resistance (Differential)
25°C
20
k
Input Capacitance
25°C
1.5
pF
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Full
1.2
3.6
1.2
3.6
1.2
3.6
V
Logic 0 Voltage
Full
0
0.3
V
Input Resistance
25°C
30
k
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (CSB)
Logic 1 Voltage
Full
1.2
3.6
1.2
3.6
1.2
3.6
V
Logic 0 Voltage
Full
0
0.3
V
Input Resistance
25°C
70
k
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Full
1.2
DRVDD+ 0.3
1.2
DRVDD+ 0.3
1.2
DRVDD+0.3
V
Logic 0 Voltage
Full
0
0.3
0
0.3
0
0.3
V
Input Resistance
25°C
30
k
Input Capacitance
25°C
2
pF
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Full
1.79
V
Logic 0 Voltage (IOL = 50 μA)
Full
0.05
V
DIGITAL OUTPUTS (D + x, D x),
(ANSI-644)1
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
247
454
247
454
247
454
mV
Output Offset Voltage (VOS)
Full
1.125
1.375
1.125
1.375
1.125
1.375
V
Output Coding (Default)
Offset binary
DIGITAL OUTPUTS (D + x, D x),
(Low Power, Reduced Signal
Option)1
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
150
250
150
250
150
250
mV
Output Offset Voltage (VOS)
Full
1.10
1.30
1.10
1.30
1.10
1.30
V
Output Coding (Default)
Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO pins sharing the same connection.
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