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| 型号： | AD9251BCPZ-20 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 20MSPS 64LFCSP |
| 标准包装： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 20M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 77mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 输入数目和类型： | 4 个单端，单极；2 个差分，单极 |
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AD9251
Rev. A | Page 25 of 36
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
excellent jitter performance.
100
0.1F
240
240
50k
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
07
938
-0
19
ADC
AD951x
PECL DRIVER
Figure 52. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 53. The AD9510/
clock drivers offer excellent jitter performance.
100
0.1F
50k
50k
CLK–
CLK+
ADC
CLOCK
INPUT
CLOCK
INPUT
0
793
8-
020
AD951x
LVDS DRIVER
Figure 53. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK pin to ground with a 0.1 μF capacitor (see
OPTIONAL
100
0.1F
50
1
150
RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
VCC
1k
1k
CLOCK
INPUT
07
93
8-
02
1
AD951x
CMOS DRIVER
Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Input Clock Divider
The AD9251 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
Optimum performance is obtained by enabling the internal
duty cycle stabilizer (DCS) when using divide ratios other than
1, 2, or 4.
The AD9251 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the
clock divider to be resynchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9251 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9251. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 55.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
80
75
70
65
60
55
50
40
45
10
20
30
40
50
60
70
80
POSITIVE DUTY CYCLE (%)
SN
R
(
d
B
F
S
)
07
93
8-
0
53
DCS ON
DCS OFF
Figure 55. SNR vs. DCS On/Off
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| AD9251BCPZ-80 | 功能描述:IC ADC 14BIT 80MSPS 64LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| AD9251BCPZ-80 | 制造商:Analog Devices 功能描述:IC ADC 14BIT 80MSPS LFCSP-64 制造商:Analog Devices 功能描述:IC, ADC, 14BIT, 80MSPS, LFCSP-64 |
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