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参数资料
| 型号： | AD9262BCPZRL7-5 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 5MHZ 64LFCSP |
| 设计资源： | Interfacing ADL5382 to AD9262 as an RF-to-Bits Solution (CN0062) |
| 标准包装： | 750 |
| 位数： | 16 |
| 采样率（每秒）： | 160M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 703mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，双极；1 个差分，单极 |
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AD9262
Rev. A | Page 25 of 32
Table 20 shows the corresponding threshold level in dBFS vs.
register setting. If the input signal crosses this level, the ORx pin
is set. In the case where 0x111[5:0] is set to all 0s, the threshold
level is set to the maximum code of 32,76710. This feature pro-
vides a means of reporting the instantaneous amplitude as it
crosses a user-provided threshold. This gives the user a sense
of the signal level without needing to perform a full power
measurement.
The user has the ability to select how the overrange conditions
are reported, and this is controlled through Register 0x111 via
AUTORST, OR_IND, and ORTHRESH (see Table 21). By
enabling the AUTORST bit, Register 0x111[7], if an overrange
occurs, the ADC automatically resets itself. The ORx pins remain
high until the automatic reset has completed. If an analog trip
occurs, the modulator resets itself after 16 consecutive clock
cycles of overrange.
If the AD9262 is used in a system that incorporates automatic
gain control (AGC), the ORx signal can be used to indicate that
the signal amplitude should be reduced. This may be particularly
effective for use in maximizing the signal dynamic range if the
signal includes high occurrence components that occasionally
exceed full scale by a small amount.
TIMING
The AD9262 provides a data clock out (DCO) pin to assist in
capturing the data in an external register. The data outputs are
valid on the rising edge of DCO, unless changed by setting
Serial Register 0x16[7] (see the Serial Port Interface (SPI)
section). See Figure 2 for a graphical timing description.
Table 20. OR Threshold Levels
0x111[5:0]
Threshold (dBFS)
0x111[5:0]
Threshold (dBFS)
0x111[5:0]
Threshold (dBFS)
1
36.12
16
9.28
2B
3.45
2
30.10
17
8.89
2C
3.25
3
26.58
18
8.52
2D
3.06
4
24.08
19
8.16
2E
2.87
5
22.14
1A
7.82
2F
2.68
6
20.56
1B
7.50
30
2.50
7
19.22
1C
7.18
31
2.32
8
18.06
1D
6.88
32
2.14
9
17.04
1E
6.58
33
1.97
A
16.12
1F
6.30
34
1.80
B
15.29
20
6.02
35
1.64
C
14.54
21
5.75
36
1.48
D
13.84
22
5.49
37
1.32
E
13.20
23
5.24
38
1.16
F
12.60
24
5.00
39
1.00
10
12.04
25
4.76
3A
0.86
11
11.51
26
4.53
3B
0.71
12
11.02
27
4.30
3C
0.56
13
10.56
28
4.08
3D
0.42
14
10.10
29
3.87
3E
0.28
15
9.68
2A
3.66
3F
0.14
Table 21. ORx Conditions
ORx Conditions
AUTORST
OR_IND
ORTHRESH[5:0]
ORTHRESH[4:0]
Description
Normal, Reset Off
0
00000
Digital trip: if 16-bit output > 32,767, ORx = 1, else ORx = 0
Digital Threshold,
Reset Off
0
>0
Digital threshold: if 16-bit output > ORTHRESH, ORx = 1,
else ORx = 0
Full Overrange,
Reset Off
0
1
0
X
If analog trip or digital trip, ORx = 1, else ORx = 0
Data Valid, No Reset
0
1
X
If analog trip or digital trip or calibration, ORx = 0, else ORx = 1
Normal, Reset On
1
0
00000
Digital trip: if 16-bit output > 32,767, ORx = 1, else ORx = 0
Digital Threshold,
Reset On
1
0
>0
Digital threshold: if 16-bit output > ORTHRESH, ORx = 1,
else ORx = 0
Full Overrange,
Reset On
1
0
X
If analog trip or digital trip ORx = 1 else ORx = 0
Data Valid,
Reset On
1
X
If analog trip or digital trip or calibration, ORx = 0 else ORx = 1
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