参数资料
型号: AD9262BCPZRL7-5
厂商: Analog Devices Inc
文件页数: 9/32页
文件大小: 0K
描述: IC ADC 16BIT 5MHZ 64LFCSP
设计资源: Interfacing ADL5382 to AD9262 as an RF-to-Bits Solution (CN0062)
标准包装: 750
位数: 16
采样率(每秒): 160M
数据接口: 串行,SPI?
转换器数目: 2
功率耗散(最大): 703mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 带卷 (TR)
输入数目和类型: 2 个单端,双极;1 个差分,单极
AD9262
Rev. A | Page 17 of 32
Input Common Mode
The analog inputs of the AD9262 are not internally dc biased. In
ac-coupled applications, the user must provide this bias externally.
Setting the device such that VCM = AVDD is recommended for
optimum performance. The analog inputs are 500 Ω resistors,
and the internal reference loop aims to develop 0.5 V across
each input resistor (see Figure 44). With 0 V differential input,
the driver sources 1 mA into each analog input.
TO LOOP FILTER
STAGE 2
DAC
AVDD – 0.5V
500
VIN+x
VIN–x
FROM QUANTIZER
VCM =AVDD
VIN p-p = 2V
0
7
772
-04
0
Figure 44. Input Common Mode
Differential Input Configurations
The AD9262 can also be configured for differential inputs. The
ADA4937-2 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the ADA4937-2 is easily set by connecting AVDD to
the VOCM2 pin of the ADA4937-2 (see Figure 45). The noise and
linearity of the ADA4937-2 need important consideration because
the system performance may be limited by the ADA4937-2.
11
6
7
13
12
9
15
200
60.4
49.9
50
SIGNAL
SOURCE
2V p-p
RT
60.4
VS
VIN–x
VIN+x
0.1F
+5V
AVDD
–5V
+1.8V
ADA4937-2
AD9262
VOCM2
07
77
2-
04
1
Figure 45. Differential Input Configuration Using the ADA4937-2
For frequencies offset from dc, where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 46. The center
tap of the secondary winding of the transformer is connected to
AVDD to bias the analog input.
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a couple of megahertz (MHz), and excessive signal power
can cause core saturation, which leads to distortion.
50
SIGNAL
SOURCE
2V p-p
1:1
RT
50
VS
VIN–x
VIN+x
0.1F
AVDD
AD9262
07
77
2-
0
42
Figure 46. Differential Transformer Configuration
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9262. The reference voltage should be decoupled to minimize
the noise bandwidth using a 10 μF capacitor. The reference is
used to generate a bias current into a matched resistor such that,
when used to bias the current in the feedback DAC, a voltage
of AVDD 0.5 V is developed at the internal side of the input
resistors (see Figure 47). The current bias circuit should also be
decoupled on the CFILT pin with a 10 μF capacitor. For this
reason, the VREF voltage should always be 0.5 V.
AVDD
AVDD – 0.5V
CFILT
AVDD – 0.5V
500
TO LOOP
FILTER
STAGE 2
500
VIN+x
VCM =AVDD
VIN p-p = 2V
VIN–x
500
10k
10F
0.5V
VREF
10F
REF
0
7772-
04
3
Figure 47. Voltage Reference Loop
Internal Reference Connection
To minimize thermal noise, the internal reference on the AD9262
is an unbuffered 0.5 V. It has an internal 10 kΩ series resistor,
which, when externally decoupled with a 10 μF capacitor, limits
the noise (see Figure 48). The unbuffered reference should not
be used to drive any external circuitry. The internal reference is
used by default and when Serial Register 0x18[6] is reset.
10k
2.85k
8.5k
3.5k
0.5V
TO CURRENT
GENERATOR
10F
0
777
2-
0
44
Figure 48. Internal Reference Configuration
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