参数资料
型号: AD9262BCPZRL7-5
厂商: Analog Devices Inc
文件页数: 25/32页
文件大小: 0K
描述: IC ADC 16BIT 5MHZ 64LFCSP
设计资源: Interfacing ADL5382 to AD9262 as an RF-to-Bits Solution (CN0062)
标准包装: 750
位数: 16
采样率(每秒): 160M
数据接口: 串行,SPI?
转换器数目: 2
功率耗散(最大): 703mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 带卷 (TR)
输入数目和类型: 2 个单端,双极;1 个差分,单极
AD9262
Rev. A | Page 31 of 32
Register
Address
Bit(s)
Mnemonic
Default
Description
Output Modes
0x14
7
DRVSTD
0
0: 3.3 V
1: 1.8 V
5
Interleave
0
1: interleave both channels onto D[15:0]A
4
OUTENB
0
1: data outputs tristated
2
OUTINV
0
1: data outputs bitwise inverted
[1:0]
Format
0
0: offset binary
1: twos complement
2: Gray code
3: offset binary
Output Adjust
0x15
[3:2]
DRVSTR33
0
Typical output sink current to DGND
0: 33 mA
1: 63 mA
2: 93 mA
3: 120 mA
[1:0]
DRVSTR18
2
Typical output sink current to DGND
0: 10 mA
1: 20 mA
2: 30 mA
3: 39 mA
Output Clock
0x16
7
DCOINV
0
1: invert DCO
Reference
0x18
6
EXTREF
0
1: use external reference
Output Data
0x101
6
QEC
0
1: enable quadrature error correction
[5:0]
KOUT
0
Output data rate, see Table 18
Overrange
0x111
7
AUTORST
0
1: enable loop filter reset indicator on ORx pin
6
OR_IND
0
[5:0]
ORTHRESH
0
QEC1
0x112
5
DCFRZ
0
1: freeze dc correction coefficients
4
PHASEFRZ
0
1: freeze phase correction coefficients
3
GAINFRZ
0
1: freeze gain correction coefficients
2
DCENB
0
1: disable dc correction
1
PHASEENB
0
1: disable phase correction
0
GAINENB
0
1: disable gain correction
QEC2
0x113
2
DCFRC
0
1: force dc correction coefficients to initial static values
1
PHASEFRC
0
1: force phase correction coefficients to initial static values
0
GAINFRC
0
1: force gain correction coefficients to initial static values
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