参数资料
| 型号： | AD9279BBCZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 80MSPS 144CSPBGA |
| 标准包装： | 1 |
| 类型： | AAF，ADC，解调器，LNA，VGA |
| 分辨率（位）： | 12 b |
| 采样率（每秒）： | 80M |
| 数据接口： | 串行，SPI? |
| 电压电源： | 模拟和数字 |
| 电源电压： | 1.7 V ~ 1.9 V，2.7 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LFBGA，CSPBGA |
| 供应商设备封装： | 144-CSPBGA（10x10） |
| 包装： | 托盘 |
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AD9279
Rev. 0 | Page 27 of 44
Tuning is normally off to avoid changing the capacitor settings
during critical times. The tuning circuit is enabled through the
SPI. It is disabled automatically after 512 cycles of the ADC
sample clock. Initializing the tuning of the filter must be
performed after initial power-up and after reprogramming the
filter cutoff scaling or ADC sample rate.
A total of eight SPI-programmable settings allows the user to
vary the high-pass filter cutoff frequency as a function of the
low-pass cutoff frequency. Two examples are shown in Table 11:
one is for an 8 MHz low-pass cutoff frequency, and the other is
for an 18 MHz low-pass cutoff frequency. In both cases, as the
ratio decreases, the amount of rejection on the low-end fre-
quencies increases. Therefore, making the entire AAF frequency
pass band narrow can reduce low frequency noise or maximize
dynamic range for harmonic processing.
Table 11. SPI-Selectable High-Pass Filter Cutoff Options
High-Pass Cutoff Frequency
SPI Setting
Ratio1
Low-Pass
Cutoff = 8 MHz
Low-Pass
Cutoff = 18 MHz
0
12.00
670 kHz
1.5 MHz
1
8.57
930 kHz
2.1 MHz
2
6.67
1.2 MHz
2.7 MHz
3
5.46
1.47 MHz
3.3 MHz
4
4.62
1.73 MHz
3.9 MHz
5
4.00
2.0 MHz
4.5 MHz
6
3.53
2.27 MHz
5.1 MHz
7
3.16
2.53 MHz
5.7 MHz
1 Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency.
ADC
The AD9279 uses a pipelined ADC architecture. The quantized
output from each stage is combined into a 12-bit result in the
digital correction logic. The pipelined architecture permits the
first stage to operate on a new input sample and the remaining
stages to operate on preceding samples. Sampling occurs on the
rising edge of the clock.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and output clocks.
Clock Input Considerations
For optimum performance, the AD9279 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
Figure 53 shows the preferred method for clocking the AD9279.
A low jitter clock source, such as the Valpey Fisher oscillator,
VFAC3-BHL-50 MHz, is converted from single-ended to differ-
ential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9279 to approximately 0.8 V p-p differential. This
helps to prevent the large voltage swings of the clock from
feeding through to other portions of the AD9279, and it
preserves the fast rise and fall times of the signal, which are
critical to low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSM2812
3.3V
50
100
CLK–
CLK+
AD9279
MINI-CIRCUITS
ADT1-1WT, 1:1Z
XFMR
VFAC3
OUT
0
94
23
-05
5
Figure 53. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac-couple
a differential PECL signal to the sample clock input pins, as
shown in Figure 54. The AD951x family of clock drivers offers
excellent jitter performance.
100
0.1F
240
240
AD951x FAMILY
CLK
*50
RESISTOR IS OPTIONAL.
PECL DRIVER
3.3V
OUT
VFAC3
09
42
3-
0
56
CLK–
CLK+
AD9279
50
*
Figure 54. Differential PECL Sample Clock
100
0.1F
AD951x FAMILY
CLK
*50
RESISTOR IS OPTIONAL.
LVDS DRIVER
3.3V
OUT
VFAC3
09
42
3-
0
57
CLK–
CLK+
AD9279
50
*
Figure 55. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 56). Although the
CLK+ input circuit supply is AVDD1 (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
selection of the drive logic voltage very flexible.
0.1F
OPTIONAL
100
0.1F
39k
CMOS DRIVER
0.1F
CLK
*50
RESISTOR IS OPTIONAL.
AD951x FAMILY
3.3V
OUT
VFAC3
09
42
3-
05
8
CLK–
CLK+
AD9279
50
*
Figure 56. Single-Ended 1.8 V CMOS Sample Clock
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