参数资料
| 型号： | AD9279BBCZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 80MSPS 144CSPBGA |
| 标准包装： | 1 |
| 类型： | AAF，ADC，解调器，LNA，VGA |
| 分辨率（位）： | 12 b |
| 采样率（每秒）： | 80M |
| 数据接口： | 串行，SPI? |
| 电压电源： | 模拟和数字 |
| 电源电压： | 1.7 V ~ 1.9 V，2.7 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LFBGA，CSPBGA |
| 供应商设备封装： | 144-CSPBGA（10x10） |
| 包装： | 托盘 |
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AD9279
Rev. 0 | Page 30 of 44
09
42
3-
06
4
CH1 500mV/DIV = DCO
CH2 500mV/DIV = DATA
CH3 500mV/DIV = FCO
5.0ns/DIV
Figure 62. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on regular FR-4 material
lengths exceeding 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position; therefore,
the user must determine whether the waveforms meet the timing
budget of the design when the trace lengths exceed 24 inches.
Additional SPI options allow the user to further increase the
internal termination (and, therefore, increase the current) of all
eight outputs to drive longer trace lengths (see Figure 65). Even
though this produces sharper rise and fall times on the data
edges, is less prone to bit errors, and improves frequency
distribution (see Figure 65), the power dissipation of the
DRVDD supply increases when this option is used.
In cases that require increased driver strength to the DCO± and
FCO± outputs because of load mismatch, Register 0x15 allows
the user to double the drive strength. To do this, set the appro-
priate bit in Register 0x05. Note that this feature cannot be used
with Bits[5:4] in Register 0x15 because these bits take precedence
over this feature. See Table 19 for more details.
The format of the output data is offset binary by default. Table 12
provides an example of the output coding format. To change the
output data format to twos complement, see the Memory Map
section.
Table 12. Digital Output Coding
Code
(VIN+) (VIN),
Input Span = 2 V p-p (V)
Digital Output
Offset Binary (D11 to D0)
4095
+1.00
1111 1111 1111
2048
0.00
1000 0000 0000
2047
0.000488
0111 1111 1111
0
1.00
0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 960 Mbps
(12 bits × 80 MSPS = 960 Mbps). The lowest typical conversion
rate is 10 MSPS, but the PLL can be set up for encode rates as
low as 5 MSPS via the SPI if lower sample rates are required for
a specific application. See Table 19 for details on enabling this
feature.
09
42
3-
0
65
600
400
–200
200
–100
100
–400
–600
0
–1.5ns
–0.5ns
–1.0ns
0ns
0.5ns
1.0ns
1.5ns
E
Y
E
DI
AG
RA
M
V
O
L
T
AG
E
(V
)
EYE: ALL BITS
ULS: 2398/2398
25
0
5
10
15
20
–200ps
–100ps
0ps
100ps
200ps
TI
E
J
ITT
E
R
H
IS
T
OGR
A
M
(
H
it
s
)
Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Less Than 24 Inches on Standard FR-4
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