参数资料
型号: AD9512BCPZ
厂商: Analog Devices Inc
文件页数: 18/48页
文件大小: 0K
描述: IC CLOCK DIST 5OUT PLL 48LFCSP
标准包装: 1
类型: 扇出缓冲器(分配),除法器
PLL:
输入: 时钟
输出: CMOS,LVDS,LVPECL
电路数: 1
比率 - 输入:输出: 2:5
差分 - 输入:输出: 是/是
频率 - 最大: 1.2GHz
除法器/乘法器: 是/无
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘,CSP
供应商设备封装: 48-LFCSP-VQ(7x7)
包装: 托盘
AD9512
Rev. A | Page 25 of 48
DIVIDERS
Each of the five clock outputs of the AD9512 has its own
divider. The divider can be bypassed to get an output at the
same frequency as the input (1×). When a divider is bypassed, it
is powered down to save power.
All integer divide ratios from 1 to 32 may be selected. A divide
ratio of 1 is selected by bypassing the divider.
Each divider can be configured for divide ratio, phase, and duty
cycle. The phase and duty cycle values that can be selected
depend on the divide ratio that is chosen.
Setting the Divide Ratio
The divide ratio is determined by the values written via the SCP
to the registers that control each individual output, OUT0 to
OUT4. These are the even numbered registers beginning at 4Ah
and going through 52h. Each of these registers is divided into
bits that control the number of clock cycles the divider output
stays high (high_cycles <3:0>) and the number of clock cycles
the divider output stays low (low_cycles <7:4>). Each value is 4
bits and has the range of 0 to 15.
The divide ratio is set by
Divide Ratio = (high_cycles + 1) + (low_cycles + 1)
Example 1:
Set the Divide Ratio = 2
high_cycles = 0
low_cycles = 0
Divide Ratio = (0 + 1) + (0 + 1) = 2
Example 2:
Set Divide Ratio = 8
high_cycles = 3
low_cycles = 3
Divide Ratio = (3 + 1) + (3 + 1) = 8
Note that a Divide Ratio of 8 may also be obtained by setting:
high_cycles = 2
low_cycles = 4
Divide Ratio = (2 + 1) + (4 + 1) = 8
Although the second set of settings produces the same divide
ratio, the resulting duty cycle is not the same.
Setting the Duty Cycle
The duty cycle and the divide ratio are related. Different divide
ratios have different duty cycle options. For example, if Divide
Ratio = 2, the only duty cycle possible is 50%. If the Divide
Ratio = 4, the duty cycle can be 25%, 50%, or 75%.
The duty cycle is set by
Duty Cycle = (high_cycles + 1)/[(high_cycles + 1) + (low_cycles + 1)]
See Table 12 for the values of the available duty cycles for each
divide ratio.
Table 12. Duty Cycle and Divide Ratio
4Ah to 52h
Divide Ratio
Duty Cycle (%)
LO<7:4>
HI<3:0>
2
50
0
3
67
0
1
3
33
1
0
4
50
1
4
75
0
2
4
25
2
0
5
60
1
2
5
40
2
1
5
80
0
3
5
20
3
0
6
50
2
6
67
1
3
6
33
3
1
6
83
0
4
6
17
4
0
4Ah to 52h
Divide Ratio
Duty Cycle (%)
LO<7:4>
HI<3:0>
7
57
2
3
7
43
3
2
7
71
1
4
7
29
4
1
7
86
0
5
7
14
5
0
8
50
3
8
63
2
4
8
38
4
2
8
75
1
5
8
25
5
1
8
88
0
6
8
13
6
0
9
56
3
4
9
44
4
3
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