参数资料
| 型号： | AD9512BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/48页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIST 5OUT PLL 48LFCSP |
| 标准包装： | 1 |
| 类型： | 扇出缓冲器（分配），除法器 |
| PLL： | 无 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:5 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
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AD9512
Rev. A | Page 31 of 48
05287-
038
3.5mA
OUT
OUTB
Figure 28. LVDS Output Simplified Equivalent Circuit
POWER-DOWN MODES
Chip Power-Down or Sleep Mode—PDB
The PDB chip power-down turns off most of the functions and
currents in the AD9512. When the PDB mode is enabled, a chip
power-down is activated by taking the FUNCTION pin to a
logic low level. The chip remains in this power-down state until
PDB is brought back to logic high. When woken up, the
AD9512 returns to the settings programmed into its registers
prior to the power-down, unless the registers are changed by
new programming while the PDB mode is active.
The PDB power-down mode shuts down the currents on the
chip, except the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. This is needed to protect the
LVPECL output circuitry from damage that could be caused by
certain termination and load configurations when tri-stated.
Because this is not a complete power-down, it can be called
sleep mode.
When the AD9512 is in a PDB power-down or sleep mode, the
chip is in the following state:
All clocks and sync circuits are off.
All dividers are off.
All LVDS/CMOS outputs are off.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
If the AD9512 clock outputs must be synchronized to each
other, a SYNC (see the Single-Chip Synchronization section) is
required when exiting power-down mode.
Distribution Power-Down
The distribution section can be powered down by writing 1 to
Register 58h<3>. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
<00>, it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down. If
the LVPECL power-down mode is set to <11b>, the LVPECL
output is not protected from reverse bias and can be damaged
under certain termination conditions.
Individual Clock Output Power-Down
Any of the five clock distribution outputs may be powered
down individually by writing to the appropriate registers via the
SCP. The register map details the individual power-down
settings for each output. The LVDS/CMOS outputs may be
powered down, regardless of their output load configuration.
The LVPECL outputs have multiple power-down modes
(see Register 3Dh, Register 3Eh, and Register 3Fh in Table 18).
These give some flexibility in dealing with various output
termination conditions. When the mode is set to <10b>, the
LVPECL output is protected from reverse bias to 2 VBE + 1 V. If
the mode is set to <11b>, the LVPECL output is not protected
from reverse bias and can be damaged under certain
termination conditions. This setting also affects the operation
when the distribution block is powered down with Register
58h<3> = 1b (see the Distribution Power-Down section).
Individual Circuit Block Power-Down
Several of the AD9512 circuit blocks (such as CLK1 and CLK2)
can be powered down individually. This gives flexibility in
configuring the part for power savings when all chip
functionality is not needed.
RESET MODES
The AD9512 has several ways to force the chip into a reset
condition.
Power-On Reset—Start-Up Conditions when VS is
Applied
A power-on reset (POR) is issued when the VS power supply is
turned on. This initializes the chip to the power-on conditions
that are determined by the default register settings. These are
indicated in the default value column of Table 17.
Asynchronous Reset via the FUNCTION Pin
As mentioned in the FUNCTION Pin section, a hard reset,
RESETB: 58h<6:5> = 00b (Default), restores the chip to the
default settings.
Soft Reset via the Serial Port
The serial control port allows a soft reset by writing to
Register 00h<5> = 1b. When this bit is set, the chip executes a
soft reset. This restores the default values to the internal
registers, except for Register 00h itself.
This bit is not self-clearing. The bit must be written to
00h<5> = 0b for the operation of the part to continue.
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相关代理商/技术参数 |
参数描述 |
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| AD9512BCPZ-REEL7 | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9512-EP | 制造商:AD 制造商全称:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Five Outputs |
| AD9512-PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| AD9512UCPZ-EP | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9512UCPZ-EP-R7 | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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