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参数资料
| 型号： | AD9515/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 23/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL CLOCK 2CH AD9515 |
| 设计资源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) AD9513/14/15 Eval Brd Schematics AD9513/14/15 Gerber Files AD9515 Eval Brd BOM |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟分配 |
| 已用 IC / 零件： | AD9515 |
| 已供物品： | 板 |
| 相关产品： | AD9515BCPZ-ND - IC CLOCK DIST 2OUT PLL 32LFCSP AD9515BCPZ-REEL7-ND - IC CLOCK DIST 2OUT PLL 32LFCSP |
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AD9515
Data Sheet
Rev. A | Page 4 of 28
TIMING CHARACTERISTICS
CLK input slew rate = 1 V/ns or greater.
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL
Termination = 50 to V
S 2 V
Output Rise Time, t
RP
60
100
ps
20% to 80%, measured differentially
Output Fall Time, t
FP
60
100
ps
80% to 20%, measured differentially
PROPAGATION DELAY, t
PECL, CLK-TO-LVPECL OUT
Divide = 1
355
480
635
ps
Divide = 2 32
395
530
710
ps
Variation with Temperature
0.5
ps/°C
OUTPUT SKEW, LVPECL OUTPUT
LVPECL OUT Across Multiple Parts, t
SKP_AB3
125
ps
LVDS
Termination = 100 differential
Output Rise Time, t
RL
200
350
ps
20% to 80%, measured differentially
Output Fall Time, t
FL
210
350
ps
80% to 20%, measured differentially
PROPAGATION DELAY, t
LVDS, CLK-TO-LVDS OUT
Delay off on OUT4
OUT3 to OUT4
Divide = 1
1.00
1.25
1.55
ns
Divide = 2 32
1.05
1.30
1.60
ns
Variation with Temperature
0.9
ps/°C
OUTPUT SKEW, LVDS OUTPUT
Delay off on OUT4
LVDS OUT Across Multiple Parts, t
SKV_AB
230
ps
CMOS
B outputs are inverted; termination = open
Output Rise Time, t
RC
650
865
ps
20% to 80%; C
LOAD = 3 pF
Output Fall Time, t
FC
650
990
ps
80% to 20%; C
LOAD = 3 pF
PROPAGATION DELAY, t
CMOS, CLK-TO-CMOS OUT
Delay off on OUT4
Divide = 1
1.10
1.45
1.75
ns
Divide = 2 32
1.15
1.50
1.80
ns
Variation with Temperature
1
ps/°C
OUTPUT SKEW, CMOS OUTPUT
Delay off on OUT4
CMOS OUT Across Multiple Parts, t
SKC_AB
300
ps
LVPECL-TO-LVDS OUT
Everything the same; different logic type
Output Delay, t
SKP_V
700
970
1150
ps
LVPECL to LVDS on same part
LVPECL-TO-CMOS OUT
Everything the same; different logic type
Output Delay, t
SKP_C
0.88
1.14
1.43
ns
LVPECL to CMOS on same part
DELAY ADJUST (OUT2; LVDS AND CMOS)
S0 = 1/3
0.34
ns
Zero Scale Variation with Temperature
0.20
ps/°C
Full Scale Time Delay2
1.7
ns
Full Scale Variation with Temperature
0.38
ps/°C
S0 = 2/3
Zero Scale Delay Time2
0.45
ns
Zero Scale Variation with Temperature
0.31
ps/°C
Full Scale Time Delay2
5.9
ns
Full Scale Variation with Temperature
1.3
ps/°C
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD95160 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Channel Clock Generator with Integrated 2.8 GHz VCO |
| AD9516-0 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.8 GHz VCO |
| AD9516-0/PCBZ | 功能描述:IC CLOCK GEN 2.8GHZ VCO 64-LFCSP RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9516-0_07 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.8 GHz VCO |
| AD9516-0BCPZ | 功能描述:IC CLOCK GEN 2.8GHZ VCO 64-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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