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| 型号： | AD9520-1/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/80页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9520-1 |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9520-1 |
| 主要属性： | 12 LVPECL/24 CMOS 输出时钟发生器，带 2.5 GHz VCO |
| 次要属性： | SPI 和 I2C 兼容控制端口 |
| 已供物品： | 板，线缆，CD，电源 |
| 产品目录页面： | 776 (CN2011-ZH PDF) |
| 相关产品： | AD9520-1BCPZ-REEL7-ND - IC CLOCK GEN 2.5GHZ VCO 64LFCSP AD9520-1BCPZ-ND - IC CLOCK GEN 2.5GHZ VCO 64LFCSP |
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Data Sheet
AD9520-1
Rev. A | Page 35 of 80
On-Chip VCO
The AD9520 includes an on-chip VCO covering the frequency
range shown in Table 2. The calibration procedure ensures that
the VCO operating voltage is centered for the desired VCO
frequency. The VCO must be calibrated when the VCO loop
is first set up, as well as any time the nominal VCO frequency
changes. However, once the VCO is calibrated, the VCO has
sufficient operating range to stay locked over temperature and
voltage extremes without needing additional calibration. See the
VCO Calibration section for additional information.
The on-chip VCO is powered by an on-chip, low dropout (LDO),
linear voltage regulator. The LDO provides some isolation of
the VCO from variations in the power supply voltage level. The
BYPASS pin should be connected to ground by a 220 nF capacitor
to ensure stability. This LDO employs the same technology that
is used in the anyCAP line of regulators from Analog Devices, Inc.,
making it insensitive to the type of capacitor used. Driving an
external load from the BYPASS pin is not supported.
PLL External Loop Filter
When using the internal VCO, reference the external loop filter
to the BYPASS pin for optimal noise and spurious performance.
Figure 39 shows an example of an external loop filter for the PLL.
This third-order design usually offers the best performance. A loop
filter must be calculated for each desired PLL configuration. The
component values depend upon the VCO frequency, the KVCO, the
PFD frequency, the CP current, the desired loop bandwidth, and
the desired phase margin. The loop filter affects the phase noise,
loop settling time, and loop stability. A knowledge of PLL theory
is necessary for understanding loop filter design. Available tools,
such as ADIsimCLK, can help with the calculation of a loop
filter according to the application requirements.
LF
VCO
CHARGE
PUMP
CP
BYPASS
C1
C2
C3
R1
31pF
R2
CBP = 220nF
AD9520
07214-
142
Figure 39. Example of External Loop Filter for a PLL Using the Internal VCO
When using an external VCO, ensure that the external loop
filter is referenced to ground. See Figure 40 for an example of an
external loop filter for a PLL using an external VCO.
CLK/CLK
EXTERNAL
VCO/VCXO
CHARGE
PUMP
CP
C1
C2
C3
R1
R2
AD9520
07214-
143
Figure 40. Example of External Loop Filter for a PLL Using an External VCO
Figure 41 and Figure 42 show the typical PLL loop filters that
are used to generate the plots in Figure 30 and Figure 32,
respectively.
C1
62pF
C3
33pF
C2
240nF
C12
220nF
BYPASS
CAPACITOR
FOR LDO
R1
820
R2
390
LF
CP
BYPASS
072
14-
234
Figure 41. Typical PLL Loop Filter Used for Clock Generation
C1
1.5nF
C3
2.2nF
C2
4.7F
C12
220nF
BYPASS
CAPACITOR
FOR LDO
R1
2.1k
R2
3k
LF
CP
BYPASS
072
14-
235
Figure 42. Typical PLL Loop Filter Used for Clock Cleanup
PLL Reference Inputs
The AD9520 features a flexible PLL reference input circuit that
allows a fully differential input, two separate single-ended inputs,
or a 16.67 MHz to 33.33 MHz crystal oscillator with an on-chip
maintaining amplifier. An optional reference clock doubler can
be used to double the PLL reference frequency. The input
frequency range for the reference inputs is specified in Table 2.
Both the differential and the single-ended inputs are self-biased,
allowing for easy ac coupling of input signals.
Either a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential input and the single-ended inputs share two pins,
REFIN and REFIN (REF1 and REF2, respectively). The desired
reference input type is selected and controlled by Register 0x01C
(see Table 50 and Table 54).
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly (~100 mV, see Table 2) to
prevent chattering of the input buffer when the reference is slow
or missing. This increases the voltage swing that is required of
the driver and overcomes the offset. The differential reference
input can be driven by either ac-coupled LVDS or ac-coupled
LVPECL signals.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave.
To avoid input buffer chatter when a single-ended, ac-coupled
input signal stops toggling, the user can set Register 0x018[7]
to 1b. This shifts the dc offset bias point down 140 mV. To increase
isolation and reduce power, each single-ended input can be
independently powered down.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9520-2 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
| AD9520-2/PCBZ | 功能描述:BOARD EVAL AD9520-2 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9520-2BCPZ | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-2BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-3 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO |
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