- 您现在的位置：买卖IC网 > PDF目录16847 > AD9520-1/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9520-1 PDF资料下载
参数资料
| 型号： | AD9520-1/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 69/80页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9520-1 |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9520-1 |
| 主要属性： | 12 LVPECL/24 CMOS 输出时钟发生器，带 2.5 GHz VCO |
| 次要属性： | SPI 和 I2C 兼容控制端口 |
| 已供物品： | 板，线缆，CD，电源 |
| 产品目录页面： | 776 (CN2011-ZH PDF) |
| 相关产品： | AD9520-1BCPZ-REEL7-ND - IC CLOCK GEN 2.5GHZ VCO 64LFCSP AD9520-1BCPZ-ND - IC CLOCK GEN 2.5GHZ VCO 64LFCSP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页当前第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
Data Sheet
AD9520-1
Rev. A | Page 71 of 80
Table 55. Output Driver Control
Reg.
Addr.
(Hex) Bits
Name
Description
0x0F0 7
OUT0 format
Selects the output type for OUT0.
0: LVPECL (default).
1: CMOS.
[6:5] OUT0 CMOS
configuration
Sets the CMOS output configuration for OUT0 when Register 0x0F0[7] = 1b.
Bits[6:5]
OUT0A
OUT0B
00
01
10
11 (default)
Tristate
On
Tristate
On
Tristate
On
[4:3] OUT0 polarity
Sets the output polarity for OUT0.
Bit 7
Bit 4
Bit 3
Output Type
OUT0A
OUT0B
0 (default)
0
1
X
0 (default)
0
1
0 (default)
1
0
1
0
1
LVPECL
CMOS
Noninverting
Inverting
Noninverting
Inverting
Noninverting
Inverting
Noninverting
Inverting
Noninverting
[2:1] OUT0 LVPECL
differential
voltage
Sets the LVPECL output differential voltage (VOD).
Bit 2
Bit 1
VOD (mV)
0
1 (default)
1
0
1
0 (default)
1
400
600
780
960
0
OUT0 LVPECL
power-down
LVPECL power-down.
0: normal operation (default).
1: safe power-down.
0x0F1 [7:0] OUT1 control
This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.
0x0F2 [7:0] OUT2 control
This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.
0x0F3 [7:0] OUT3 control
This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.
0x0F4 [7:0] OUT4 control
This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.
0x0F5 [7:0] OUT5 control
This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.
0x0F6 [7:0] OUT6 control
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
0x0F7 [7:0] OUT7 control
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
0x0F8 [7:0] OUT8 control
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
0x0F9 [7:0] OUT9 control
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
0x0FA [7:0] OUT10 control
This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
0x0FB [7:0] OUT11 control
This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
0x0FC 7
CSDLD en OUT7
OUT7 is enabled only if the CSDLD signal is high.
Bit 7
CSDLD
Signal
OUT7 Enable Status
0
1
0
1
Not affected by CSDLD signal (default).
Asynchronous power-down.
Asynchronously enables OUT7 if not powered down by other settings. For this feature, use current
source digital lock detect and set the enable LD pin comparator bit (Register 0x01D[3]).
6
CSDLD en OUT6
OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
5
CSDLD en OUT5
OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
4
CSDLD en OUT4
OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
3
CSDLD en OUT3
OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
2
CSDLD en OUT2
OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
1
CSDLD en OUT1
OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0
CSDLD en OUT0
OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0x0FD [7:4] Unused
Unused.
3
CSDLD en OUT11 OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
2
CSDLD en OUT10 OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
1
CSDLD en OUT9
OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0
CSDLD en OUT8
OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
相关PDF资料 |
PDF描述 |
|---|---|
| 50PX0R47MEFC5X11 | CAP ALUM 0.47UF 50V 20% RADIAL |
| MAX675CSA+T | IC VREF SERIES PREC 5V 8-SOIC |
| 16PX47MEFC5X11 | CAP ALUM 47UF 16V 20% RADIAL |
| AD9516-3/PCBZ | BOARD EVAL FOR AD9516-3 2.0GHZ |
| RSC06DRXH-S734 | CONN EDGECARD 12POS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9520-2 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
| AD9520-2/PCBZ | 功能描述:BOARD EVAL AD9520-2 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9520-2BCPZ | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-2BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-3 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO |
发布紧急采购，3分钟左右您将得到回复。