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参数资料
| 型号： | AD9523-1BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/60页 |
| 文件大小： | 0K |
| 描述： | IC INTEGER-N CLCK GEN 72LFCSP |
| 标准包装： | 400 |
| 类型： | 时钟/频率发生器，扇出缓冲器（分配），多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，光纤通道，SONET/SDH |
| 输入： | CMOS |
| 输出： | HSTL，LVCMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:14 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1GHz |
| 电源电压： | 1.768 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 72-LFCSP |
| 包装： | 带卷 (TR) |
| 配用： | AD9523/PCBZ-ND - BOARD EVAL FOR AD9523 |
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AD9523-1
Rev. B | Page 15 of 60
Pin
No.
Mnemonic
Type1
Description
45
VDD3_OUT[6:7]
P
3.3 V Supply for Output 6 and Supply Output 7 Clock Drivers.
46
OUT6
O
Complementary Square Wave Clocking Output 6. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
47
OUT6
O
Square Wave Clocking Output 6. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
48
VDD1.8_OUT[6:7]
P
1.8 V Supply for Output 6 and Output 7 Clock Dividers.
49
OUT5
O
Complementary Square Wave Clocking Output 5. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
50
OUT5
O
Square Wave Clocking Output 5. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
51
VDD3_OUT[4:5]
P
3.3 V Supply for Output 4 and Output 5 Clock Drivers.
52
OUT4
O
Complementary Square Wave Clocking Output 4. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
53
OUT4
O
Square Wave Clocking Output 4. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
54
VDD1.8_OUT[4:5]
P
1.8 V Supply for Output 4 and Output 5 Clock Dividers.
55
STATUS1/SP1
I/O
Lock Detect and Other Status Signals (STATUS1)/I2C Address (SP1). This pin has an internal 40 kΩ pull-
down resistor.
56
STATUS0/SP0
I/O
Lock Detect and Other Status Signals (STATUS0)/I2C Address (SP0). This pin has an internal 40 kΩ pull-
down resistor.
57
EEPROM_SEL
I
EEPROM Select. Setting this pin high selects the register values stored in the internal EEPROM to be
loaded at reset and/or power-up. Setting this pin low causes the AD9523-1 to load the hard-coded
default register values at power-up/reset. This pin has an internal 40 kΩ pull-down resistor.
58
OUT3
O
Complementary Square Wave Clocking Output 3. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
59
OUT3
O
Square Wave Clocking Output 3. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
60
VDD3_OUT[2:3]
P
3.3 V Supply for Output 2 and Output 3 Clock Drivers.
61
OUT2
O
Complementary Square Wave Clocking Output 2. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
62
OUT2
O
Square Wave Clocking Output 2. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
63
VDD1.8_OUT[2:3]
P
1.8 V Supply for Output 2 and Output 3 Clock Dividers.
64
OUT1
O
Complementary Square Wave Clocking Output 1. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
65
OUT1
O
Square Wave Clocking Output 1. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
66
VDD3_OUT[0:1]
P
3.3 V Supply for Output 0 and Output 1 Clock Drivers.
67
OUT0
O
Complementary Square Wave Clocking Output 0. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
68
OUT0
O
Square Wave Clocking Output 0. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
69
VDD1.8_OUT[0:1]
P
1.8 V Supply for Output 0 and Output 1 Clock Dividers.
70
ZD_IN
I
External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input for the PLL
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
71
ZD_IN
I
Complementary External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input
for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
72
PLL1_OUT
O
Single-Ended CMOS Output from PLL1. This pin has settings for weak and strong in Register 0x1BA,
Bit 4 (see Table 52).
EP
EP, GND
GND
Exposed Paddle. The exposed paddle is the ground connection on the chip. It must be soldered
to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and
mechanical strength benefits.
1 P = power, I = input, O = output, I/O = input/output, P/O = power/output, GND = ground.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9523BCPZ | 功能描述:IC INTEGER-N CLCK GEN 72LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| AD9523BCPZ-REEL7 | 功能描述:IC INTEGER-N CLCK GEN 72LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| AD9524 | 制造商:AD 制造商全称:Analog Devices 功能描述:Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs |
| AD9524/PCBZ | 功能描述:BOARD EVAL FOR AD9524 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9524BCPZ | 功能描述:IC INTEGER-N CLCK GEN 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
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