参数资料
型号: AD9547BCPZ-REEL7
厂商: Analog Devices Inc
文件页数: 1/104页
文件大小: 0K
描述: IC CLOCK GEN/SYNCHRONIZR 64LFCSP
产品变化通告: AD9547 Mask Change 20/Oct/2010
标准包装: 750
类型: 时钟/频率发生器,同步器
PLL:
主要目的: 以太网,SONET/SDH,Stratum
输入: CMOS,LVDS,LVPECL
输出: CMOS,LVDS,LVPECL
电路数: 1
比率 - 输入:输出: 2:2
差分 - 输入:输出: 是/是
频率 - 最大: 750kHz
电源电压: 1.71 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 带卷 (TR)
Dual/Quad Input Network Clock
Generator/Synchronizer
Data Sheet
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumed byAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithout notice.No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 2009–2013 Analog Devices, Inc. Allrights reserved.
FEATURES
Supports Stratum 2stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Automatic/manual holdoverand reference switchover
2 pairs of reference input pins, with each pair configurable
as a single differential input or as 2 independent single-
ended inputs
Input reference frequencies from 1kHz to 750 MHz
Reference validation and frequency monitoring (1ppm)
Programmable input reference switchover priority
30-bit programmable input reference divider
2 pairs of clock output pins, with each pair configurable as
a single differential LVDS/LVPECL output or as 2 single-
ended CMOS outputs
Output frequencies up to 450 MHz
20-bit integer and 10-bit fractional programmable feedback
divider
Programmable digital loop filter covering loop bandwidths
from 0.001 Hz to 100 kHz
Optional low noise LC-VCO system clock multiplier
Optional crystal resonatorfor system clock input
On-chip EEPROM to store multiple power-up profiles
Software controlled power-down
64-lead LFCSP package
APPLICATIONS
Network synchronization
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 2holdover, jitter cleanup, and phase transient
control
Stratum 3E and Stratum 3reference clocks
Wireless base stations, controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9547 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9547 generates an output clock that is synchronized to one
of two differential or four single-ended external input references.
The digital PLL allows for reduction of input time jitter or phase
noise associated with the external references. The AD9547
continuously generates a clean (low jitter), valid output clock,
even when all references fail, by means of digitally controlled
loop and holdover circuitry.
The AD9547 operates over an industrial temperature range of
40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFERENCE INPUTS
AND
MONITOR MUX
STATUS AND
CONTROL PINS
SERIAL CONTROL INTERFACE
(SPI or I2C)
EEPROM
DIGITAL
PLL
CLOCK DISTRIBUTION
SYNC
DAC
CLOCK
MULTIPLIER
STABLE
SOURCE
ANALOG
FILTER
AD9547
CHANNEL 0
DIVIDER
CHANNEL 1
DIVIDER
08300-
001
Figure 1.
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