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参数资料
| 型号： | AD9547BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 47/104页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9547 Mask Change 20/Oct/2010 |
| 标准包装： | 750 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750kHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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Data Sheet
AD9547
Rev. E | Page 47 of 104
Table 28. EEPROM Controller Instruction Set
Instruction
Value (Hex)
Instruction Type
Bytes
Required
Description
0x00 to 0x7F
Data
3
A data instruction tells the controller to transfer data to or from the device settings part of
the register map. A data instruction requires two additional bytes that, together, indicate a
starting address in the register map. Encoded in the data instruction is the number of
bytes to transfer, which is one more than the instruction value.
0x80
I/O update
1
When the controller encounters this instruction while downloading from the EEPROM, it
issues a soft I/O update (see Register 0x0005 in Table 43).
0xA0
Calibrate
1
When the controller encounters this instruction while downloading from the EEPROM, it
initiates a system clock calibration sequence (see Register 0x0A02 in Table 121).
0xA1
Distribution sync
1
When the controller encounters this instruction while downloading from the EEPROM,
it issues a sync pulse to the output distribution synchronization (see Register 0x0A02 in
0xB0 to
0xCF
Condition
1
0xB1 to 0xCF are condition instructions and correspond to Condition 1 to Condition 31,
respectively. 0xB0 is the null condition instruction. See the EEPROM Conditional Processing
section for details.
0xFE
Pause
1
When the controller encounters this instruction in the scratch pad while uploading to the
EEPROM, it resets the scratch pad address pointer and holds the EEPROM address pointer
at its last value. This allows storage of more than one instruction sequence in the EEPROM.
Note that the controller does not copy this instruction to the EEPROM during upload.
0xFF
End
1
When the controller encounters this instruction in the scratch pad while uploading to the
EEPROM, it resets both the scratch pad address pointer and the EEPROM address pointer
and then enters an idle state.
When the controller encounters this instruction while downloading from the EEPROM, it
resets the EEPROM address pointer and then enters an idle state.
EEPROM Upload
To upload data to the EEPROM, first ensure that the write
enable bit (Register 0x0E00, Bit 0) is set. Then, on setting the
autoclearing save to EEPROM bit (Register 0x0E02, Bit 0), the
controller initiates the EEPROM data storage process. When
an EEPROM save/load transfer is complete, wait a minimum
of 10 μs before starting the next EEPROM save/load transfer.
Uploading EEPROM data requires that the user first write an
instruction sequence into the scratch pad registers. During the
upload process, the controller reads the scratch pad data byte by
byte, starting at Register 0x0E10 and incrementing the scratch
pad address pointer as it goes, until it reaches a pause or end
instruction.
As the controller reads the scratch pad data, it transfers the
data from the scratch pad to the EEPROM (byte by byte) and
increments the EEPROM address pointer accordingly, unless
it encounters a data instruction. A data instruction tells the
controller to transfer data from the device settings portion of
the register map to the EEPROM. The number of bytes to
transfer is encoded within the data instruction, and the starting
address for the transfer appears in the next two bytes in the
scratch pad.
When the controller encounters a data instruction, it stores the
instruction in the EEPROM, increments the EEPROM address
pointer, decodes the number of bytes to be transferred, and
increments the scratch pad address pointer. Then it retrieves
the next two bytes from the scratch pad (the target address) and
increments the scratch pad address pointer by 2. Next, the con-
troller transfers the specified number of bytes from the register
map (beginning at the target address) to the EEPROM.
When it completes the data transfer, the controller stores an extra
byte in the EEPROM to serve as a checksum for the transferred
block of data. To account for the checksum byte, the controller
increments the EEPROM address pointer by one more than the
number of bytes transferred. Note that, when the controller
transfers data associated with an active register, it actually
transfers the buffered contents of the register (see the
Buffered/Active Registers section for details on the difference
between buffered and active registers). This allows for the
transfer of nonzero autoclearing register contents.
Note that conditional processing does not occur during an upload
sequence (see the EEPROM Conditional Processing section).
EEPROM Download
An EEPROM download results in a transfer of data from the
EEPROM to the device register map. To download data, the user
sets the autoclearing load from EEPROM bit (Register 0x0E03,
Bit 1). This commands the controller to initiate the EEPROM
download process. During download, the controller reads the
EEPROM data byte by byte, incrementing the EEPROM address
pointer as it goes, until it reaches an end instruction. As the con-
troller reads the EEPROM data, it executes the stored instructions,
which includes transferring stored data to the device settings
portion of the register map whenever it encounters a data
instruction. When an EEPROM save/load transfer is complete, wait
a minimum of 10 μs before starting the next EEPROM save/load
transfer.
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