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参数资料
| 型号： | AD9547BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 43/104页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9547 Mask Change 20/Oct/2010 |
| 标准包装： | 750 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750kHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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Data Sheet
AD9547
Rev. E | Page 43 of 104
The deterministic delay, expressed as tLATENCY in the following
equation, is a function of the frequency division factor (Qn) of
the channel divider associated with the zero-delay channel.
tLATENCY = (Qn + 4) × tCLK_IN or tLATENCY = (Qn + 5) × tCLK_IN
In addition to deterministic delay, there is random delay (tPROP)
associated with the propagation of the reference signal through
the input reference receiver, as well as the propagation of the
clock signal through the clock distribution logic. The total delay is
tDELAY = tLATENCY + tPROP
The user can compensate for tDELAY by using the device’s phase
offset controls to move the edge timing of the distribution output
signal relative to the input reference edge. One method is to
use the open-loop phase offset registers (Address 0x030D and
Address 0x030E) for timing adjustment. However, be sure to
use sufficiently small phase increments to make the adjustment.
Too large a phase step can result in the clock distribution logic
missing a CLKINx edge, thus disrupting the edge alignment
process. The appropriate phase increment depends on the
transient response of any external circuitry connected between
the DACOUTx and CLKINx pins.
The other method is to use the closed-loop phase offset registers
(Address 0x030F to Address 0x0315) for timing adjustment.
However, be sure to use a sufficiently small phase vs. time profile.
Changing the phase too quickly can cause the DPLL tolose lock,
thus ruining the edge alignment process. Note that the AD9547
phase slew limit register (Address 0x0316 and 0x0317) can be
used to limit the rate of change of phase automatically, thereby
mitigating the potential loss-of-lock problem.
To guarantee synchronization of the output dividers, it is
important to make any edge timing adjustments after the
synchronization event. Furthermore, when making timing
adjustments, the distribution outputs can be disabled and then
renabled after the adjustment is complete. This prevents the
device from generating output clock signals during the timing
adjustment process.
Note that the form of zero-delay synchronization described here
does not track propagation time variations within the distribution
clock input path or the reference input path (on or off chip) over
temperature, supply, and so on. It is strictly a one-time synchro-
nization event.
Synchronization Mask
Each output channel has a dedicated synchronization mask bit
(Register 0x0402, Bits[1:0]). When the mask bit associated with
a particular channel is set, that channel does not respond to the
synchronization signal. This allows the device to operate with
the masked channels active and the unmasked channels stalled
while they wait for a synchronization pulse.
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相关代理商/技术参数 |
参数描述 |
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| AD9548 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer |
| AD9548/PCBZ | 功能描述:BOARD EVAL FOR AD9548 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9548/PCBZ | 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board |
| AD9548BCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
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