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参数资料
| 型号： | AD9547BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 102/104页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9547 Mask Change 20/Oct/2010 |
| 标准包装： | 750 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750kHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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Data Sheet
AD9547
Rev. E | Page 97 of 104
Table 151. EEPROM Storage Sequencefor DPLL Settings
Address
Bit
Bit Name
Description
0x0E18
[7:0]
DPLL
The default value of this register is 0x1B, which the controller interprets as a data instruction. Its
decimal value is 27, which tells the controller to transfer 28 bytes of data (27 + 1) beginning at the
address specifiedby the next two bytes. The controller stores 0x1B inthe EEPROM and increments the
EEPROM address pointer.
0x0E19
[7:0]
DPLL
The default value of these two registers is 0x0300. Note that Register 0x0E19 and Register 0x0E1A are
the most significant and least significant bytes of the target address, respectively. Because the
previous register contains a data instruction, these two registersdefine a startingaddress (inthis case,
0x0300). The controllerstores 0x0300inthe EEPROM and increments the EEPROM pointer by 2. It then
transfers 28bytesfrom theregister map(beginningat Address0x0300)to the EEPROM andincrements
the EEPROM address pointer by 29 (28 data bytes and one checksum byte). The 28 bytes transferred
correspond to the DPLL parameters in the register map.
0x0E1A
[7:0]
Table 152. EEPROM Storage Sequencefor Clock Distribution Settings
Address
Bit
Bit Name
Description
0x0E1B
[7:0]
Clock distribution
The default value of this register is 0x19, which the controller interprets as a data instruction. Its
decimal value is 25; this tells the controller to transfer 26 bytes of data (25 + 1) beginning at the
address specifiedby the next two bytes. The controller stores 0x19 in the EEPROM and
increments the EEPROM address pointer.
0x0E1C
[7:0]
Clock distribution
The default value of these two registers is 0x0400. Note that Register0x0E1CandRegister 0x0E1D
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0400). The controller stores 0x0400 inthe EEPROM and increments the EEPROM
pointer by 2. It then transfers 26 bytes from the register map (beginning at Address 0x0400) to
the EEPROM and incrementsthe EEPROM address pointer by 27(26 data bytes andone checksum
byte). The 26bytestransferredcorrespondto the clockdistributionparameters inthe registermap.
0x0E1D
[7:0]
0x0E1E
[7:0]
I/O update
The default value of this register is 0x80, which the controller interprets as an I/O update
instruction. Thecontrollerstores 0x80inthe EEPROM andincrements the EEPROM address pointer.
Table 153. EEPROM Storage Sequencefor Reference Input Settings
Address
Bit
Bit Name
Description
0x0E1F
[7:0]
Reference inputs
The default value of this register is 0x07, which the controller interprets as a data instruction. Its
decimalvalueis 7, whichtellsthe controller to transfereight bytesofdata (7 + 1), beginningat the
address specifiedby the next two bytes. The controller stores 0x07 inthe EEPROM and increments
the EEPROM address pointer.
0x0E20
[7:0]
Reference inputs
The default value of these two registers is 0x0500. Note that Register0x0E20andRegister 0x0E21
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0500). The controller stores 0x0500inthe EEPROM and increments the EEPROM
pointerby 2. It thentransferseightbytesfrom theregister map(beginningat Address0x0500) to the
EEPROM and increments the EEPROM address pointer by nine (eight data bytes andone checksum
byte). The eightbytestransferredcorrespondto the referenceinputsparameters intheregister map.
0x0E21
[7:0]
Table 154. EEPROM Storage Sequencefor Profile 0 and Profile 1 Settings
Address
Bit
Bit Name
Description
0x0E22
[7:0]
Profile0 andProfile 1
The default value of this register is 0x63, which the controller interprets as a data instruction. Its
decimalvalueis 99, whichtells thecontrollerto transfer 100 bytes ofdata (99 + 1), beginningat the
address specifiedby the next two bytes. The controller stores 0x63 in the EEPROM and
increments the EEPROM address pointer.
0x0E23
[7:0]
Profile0 andProfile 1
The default value of these two registers is 0x0600. Note that Register0x0E23andRegister 0x0E24
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0600). The controller stores 0x0600inthe EEPROM and increments the EEPROM
pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0600) to
the EEPROM and incrementsthe EEPROM address pointer by 101 (100data bytes andone checksum
byte). The 99 bytes transferred correspondto the Profile 0 and Profile 1 parameters inthe
register map.
0x0E24
[7:0]
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