- 您现在的位置：买卖IC网 > PDF目录1987 > AD9547BCPZ-REEL7 (Analog Devices Inc)IC CLOCK GEN/SYNCHRONIZR 64LFCSP PDF资料下载
参数资料
| 型号： | AD9547BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 46/104页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9547 Mask Change 20/Oct/2010 |
| 标准包装： | 750 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750kHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页当前第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页
AD9547
Data Sheet
Rev. E | Page 46 of 104
EEPROM
EEPROM Overview
The AD9547 contains an integrated 2048-byte electrically erasable
programmable read-only memory (EEPROM). The AD9547
can be configured to perform a download at power-up via the
multifunction pins (M3 to M7), but uploads and downloads
can also be done on demand via the EEPROM control registers
(Address 0x0E00 to Address 0x0E03).
The EEPROM provides the ability to upload and download
configuration settings to and from the register map. Figure 48
shows a functional diagram of the EEPROM.
Register 0x0E10 to Register 0x0E3F represent a 48-byte scratch
pad that enables the user to store a sequence of instructions for
transferring data to the EEPROM from the device settings portion
of the register map. Note that the default values for these registers
provide a sample sequence for saving/retrieving all of the AD9547
EEPROM-accessible registers. Figure 48 shows the connectivity
between the EEPROM and the controller that manages data
transfer between the EEPROM and the register map.
The controller oversees the process of transferring EEPROM data
to and from the register map. There are two modes of operation
handled by the controller: saving data to the EEPROM (upload
mode) or retrieving data from the EEPROM (download mode).
In either case, the controller relies on a specific instruction set.
EEPROM
(0x000 TO 0x7FF)
DA
T
A
DA
T
A
DATA
EEPROM
ADDRESS
POINTER
M7
M6
M5
M4
M3
REGISTER MAP
DEVICE SETTINGS
(0x0100 TO 0x0A10)
SCRATCH PAD
(0x0E10 TO 0x0E3F)
SERIAL
INPUT/OUTPUT
PORT
CO
NDI
T
IO
N
(0
x0E
01
[
4:
0]
)
SCRATCH PAD
ADDRESS
POINTER
DEVICE
SETTINGS
ADDRESS
POINTER
EEPROM
CONTROLLER
083
00-
024
Figure 48. EEPROM Functional Diagram
EEPROM Instructions
Table 28 lists the EEPROM controller instruction set. The
controller recognizes all instruction types, whether it is in upload or
download mode, except for the pause instruction, which it
recognizes only in upload mode.
The I/O update, calibrate, distribution sync, and end instructions
are mostly self-explanatory. The others, however, warrant further
detail, as described in the following paragraphs.
Data instructions are those that have a value from 0x00 to 0x7F.
A data instruction tells the controller to transfer data between the
EEPROM and the register map. The controller needs the following
two parameters to carry out the data transfer:
The number of bytes to transfer
The register map target address
The controller decodes the number of bytes to transfer directly
from the data instruction itself by adding one to the value of the
instruction. For example, the data instruction, 0x1A, has a decimal
value of 26; therefore, the controller knows to transfer 27 bytes
(one more than the value of the instruction). Whenever the con-
troller encounters a data instruction, it knows to read the next
two bytes in the scratch pad because these bytes contain the
register map target address.
Note that, in the EEPROM scratch pad, the two registers that
make up the address portion of a data instruction have the MSB of
the address in the D7 position of the lower register address. The
bit weight increases left to right, from the lower register address
to the higher register address. Furthermore, the starting address
always indicates the lowest numbered register map address in the
range of bytes to transfer. That is, the controller always starts at
the register map target address and counts upward, regardless of
whether the serial I/O port is operating in I2C, SPI LSB first, or
SPI MSB first mode.
As part of the data transfer process during an EEPROM upload,
the controller calculates a 1-byte checksum and stores it as the final
byte of the data transfer. As part of the data transfer process during
an EEPROM download, however, the controller again calculates
a 1-byte checksum value but compares the newly calculated check-
sum with the one that was stored during the upload process. If an
upload/download checksum pair does not match, the controller
sets the EEPROM fault status bit (Register 0x0D03, Bit 1). If the
upload/download checksums match for all data instructions
encountered during a download sequence, the controller sets
the EEPROM complete status bit (Register 0x0D03, Bit 0).
Condition instructions are those that have a value from 0xB0 to
0xCF. Condition Instruction 0xB1 to Condition Instruction 0xCF
represents Condition 1 to Condition 31, respectively. Condition
Instruction 0xB0 is special because it represents the null condition
(see the EEPROM Conditional Processing section).
A pause instruction, like an end instruction, is stored at the end
of a sequence of instructions in the scratch pad. When the control-
ler encounters a pause instruction during an upload sequence,
it keeps the EEPROM address pointer at its last value. This way,
the user can store a new instruction sequence in the scratch pad
and upload the new sequence to the EEPROM. The new sequence
is stored in the EEPROM address locations immediately following
the previously saved sequence. This process is repeatable until
an upload sequence contains an end instruction. The pause
instruction is also useful when used in conjunction with condition
processing. It allows the EEPROM to contain multiple occurrences
of the same register(s), with each occurrence linked to a set of
conditions (see the EEPROM Conditional Processing section).
相关PDF资料 |
PDF描述 |
|---|---|
| AD9548BCPZ-REEL7 | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| AD9549ABCPZ-REEL7 | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| AD9550BCPZ-REEL7 | IC INTEGER-N TRANSLATOR 32-LFCSP |
| AD9551BCPZ | IC CLOCK GEN MULTISERV 40-LFCSP |
| AD9552BCPZ-REEL7 | IC PLL CLOCK GEN LP 32LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9548 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer |
| AD9548/PCBZ | 功能描述:BOARD EVAL FOR AD9548 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9548/PCBZ | 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board |
| AD9548BCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
| AD9548BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。