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| 型号： | AD9547BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 38/104页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9547 Mask Change 20/Oct/2010 |
| 标准包装： | 750 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750kHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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Data Sheet
AD9547
Rev. E | Page 39 of 104
Bits[5:3]). The charge pump current varies from125 μA to1 mA
in 125 μA steps. The default setting is 500 μA.
SYSCLK PLLLoop Filter
The AD9547 has an internal second-order loop filter that estab-
lishes the loop dynamics for input signals between 12.5 MHz and
100 MHz. By default, the device uses the internal loop filter.
However, an external loop filter option is available by setting
the external loop filter enable bit (Register 0x0100, Bit 7). This
bit bypasses the internal loop filter and allows the device to use
an externally connected second-order loop filter, as shown in
SYSCLK_VREG
R1
AD9547
SYSCLK_LF
C1
C2
34
35
08300-
021
Figure 45. External Loop Filter Schematic
To determine the external loop filter components, the user decides
on the desired open loop bandwidth (fOL) and phase margin (φ).
These parameters allowcalculation of the loop filter components,
as follows:
R1 =
( )
φ
+
π
sin
1
VCO
CP
OL
K
I
Nf
C1 =
2
)
(
2
)
tan(
OL
VCO
CP
f
N
K
I
π
φ
C2 =
φ
π
)
cos(
)
sin(
1
)
2
(
2
OL
VCO
CP
f
N
K
I
where:
KVCO = 7 × 107 V/ns (typical).
ICP is the programmed charge pump current (amperes).
N is the programmed feedback divider value.
fOL is the desired open-loop bandwidth (Hz).
Φ is the desired phase margin (radians).
For example, assuming that N = 40, ICP = 0.5 mA, fOL = 400 kHz,
and Φ = 50°, then the loop filter calculations yield R1 = 3.31 kΩ,
C1 = 330 pF, and C2 = 50.4 pF.
SystemClock Period
Many of the user programmable parameters of the AD9547 have
absolute time units. To make this possible, the AD9547 requires
a priori knowledge of the period of the system clock. To accom-
modate this requirement, the user programs the 21-bit nominal
system clock period in the nominal SYSCLK period register
(Address 0x0103 to Address 0x0105). The contents of this register
reflect the actual period of the system clock in units of femto-
seconds (fs). The user must program this register properly to
ensure proper operation of the device because many of its
subsystems rely on this value.
SystemClock StabilityTimer
The system clock stability timer, located in Register 0x0106 to
Register 0x0108, is a 20-bit value programmed in units of milli-
seconds (ms). If the programmed timer value is 0, the timer
immediately indicates that it has timed out. If the programmed
timer value is nonzero and the SYSCLK PLL is enabled, the timer
starts timing when the SYSCLK PLL lock detector indicates lock
and times out after the prescribed period. However, when the user
disables the SYSCLK PLL, the timer ignores the SYSCLK PLL
lock detector and starts timing the instant that the SYSCLK PLL
is disabled. The user can monitor the status of the stability timer
at Register 0x0D01, Bit 4, via the multifunction pins or via the
IRQ pin.
Note that the system clock stability timer must be programmed
before the SYSCLK PLL is either activated or disabled.
SYSCLK PLLCalibration
When using the SYSCLK PLL, it is necessary to calibrate the
LC-VCO to ensure that the PLL can remain locked to the system
clock input signal. Assuming the presence of either an external
SYSCLK input signal or a crystal resonator, the calibration process
executes after the user sets and then clears the calibrate system
clock bit in the cal/sync register (Register 0x0A02, Bit 0). During
the calibration process, the device calibrates the VCO amplitude
and frequency. The status of the system clock calibration process
is user accessible via the system clock status register (Register
0x0D01, Bit 1). It is also available via the IRQ monitor register
(Bit 1 of Register 0x0D02), provided that the status bit is enabled
via the IRQ mask register (Register 0x0209 and Register 0x0210).
When the calibration sequence is complete, the SYSCLK PLL
eventually attains a lock condition, at which point the system
clock stability timer begins its countdown sequence. Expiration
of the timer indicates that the SYSCLK PLL is stable, which is
reflected in the system clock status register (Register 0x0D01, Bit 4).
Note that the monitors/detectors associated with the input
references (REF A/REF AA and REF B/REF BB) are internally
disabled until the SYSCLK PLL indicates that it is stable.
CLOCK DISTRIBUTION
The clock distribution block of the AD9547 provides an integrated
solution for generating multiple clock outputs based on frequency
dividing the DPLL output. The distribution output consists of
two channels (OUT0 and OUT1). Each channel has a dedicated
divider and output driver section, as shown in Figure 46.
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相关代理商/技术参数 |
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| AD9548 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer |
| AD9548/PCBZ | 功能描述:BOARD EVAL FOR AD9548 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
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| AD9548BCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
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