- 您现在的位置：买卖IC网 > PDF目录1987 > AD9547BCPZ-REEL7 (Analog Devices Inc)IC CLOCK GEN/SYNCHRONIZR 64LFCSP PDF资料下载
参数资料
| 型号： | AD9547BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/104页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9547 Mask Change 20/Oct/2010 |
| 标准包装： | 750 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750kHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页当前第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页
AD9547
Data Sheet
Rev. E | Page 28 of 104
DQ
R
0
1
EN
FAULTED
VALID
FORCE VALIDATION
TIMEOUT
REF FAULT
REF MONITOR
BYPASS
REF MONITOR
OVERRIDE
REGISTER CONTROL BITS
REFERENCE VALIDATION LOGIC
(4 COPIES, 1 PER REFERENCE INPUT)
REFERENCE
MONITOR
R
VALIDATION TIMER
TIMEOUT
083
00-
01
0
Figure 33. Reference Validation Override
Reference Validation Override Control
Register 0x0A0E to Register 0x0A10 provide the user with the
ability to override the reference validation logic, enabling a
certain level of troubleshooting capability. Each of the four
input references has a dedicated block of validation logic, as
shown in Figure 33. The state of the valid signal at the output
defines a particular reference as valid (1) or not valid (0), which
includes the validation period (if activated) as prescribed by the
validation timer. The override controls are the three control bits
on the left side of the diagram.
The main feature to note is that when faulted = 1, the output latch
is reset, which forces valid = 0 (indicating an invalid reference),
regardless of the state of any other signal. Under the default con-
dition (that is, all three control bits are set to 0), the reference
monitor is the primary source of the validation process. This is
because, under the default condition, the ref fault signal from the
reference monitor is identical to the faulted signal.
The function of the faulted signal is fourfold.
When faulted = 1, valid = 0, regardless of the state of any
other control signal. Therefore, faulted = 1 indicates an
invalid reference.
When the faulted signal transitions from 0 to 1 (that is, from
not faulted to faulted), the validation timer is momentarily
reset, which means that, when it is enabled, it must exhaust its
full counting sequence before it expires.
When faulted = 0 (that is, the reference is not faulted), the
validation timer is allowed to perform its timing sequence.
When faulted = 1 (that is, the reference is faulted), the
validation timer is reset and halted.
The faulted signal passes through an inverter, which converts
it to a not faulted signal that appears at the input of the valid
latch. This allows the valid latch to capture the state of the
not faulted signal when the validation timer expires.
The reference monitor bypass control bit (Address 0x0A10) enables
bypassing of the reference fault signal generated by the reference
monitor. When the reference monitor bypass bit = 1, the state of the
faulted signal is dictated by the reference monitor override control
bit. This is useful when the user relies on an external reference
monitor rather than the internal monitor resident in the device.
The user programs the reference monitor override bit based on
the status of the external monitor. On the other hand, when the
reference monitor bypass bit = 0, the reference monitor override
control bit (Address 0x0A0F) allows the user to manually test
the operation of both the valid latch and the validation timer.
In this case, the user relies on the signal generated by the internal
reference monitor (reference fault) but uses the reference monitor
override bit to emulate a faulted reference. That is, when the
reference monitor override bit = 1, faulted = 1, but when the
reference monitor override bit = 0, faulted = reference fault.
In addition, the user can emulate a timeout of the validation timer
via the force validation timeout control register at Address 0x0A0E.
Writing a Logic 1 to this autoclearing bit triggers the valid latch,
which is identically equivalent to a timeout of the validation timer.
REFERENCE PROFILES
The AD9547 has eight independent profile registers. A profile
register contains 50 bytes that establish a particular set of device
parameters. Each of the four input references can be assigned to
any one of the eight profiles (that is, more than one reference can
be assigned to the same profile). The profiles allow the user to
prescribe the specific device functionality that should take effect
when one of the input references assigned to a profile becomes the
active reference. Each profile register has the same format and
stores the following device parameters:
Reference priority
Reference period value (in femtoseconds (fs))
Inner tolerance value (1/tolerance)
Outer tolerance value (1/tolerance)
Validation timer value (milliseconds (ms))
Redetect timer value (milliseconds (ms))
Digital loop filter coefficients
Reference prescaler setting (R divider)
Feedback divider settings (S, U, and V)
DPLL phase lock detector threshold level
DPLL phase lock detector fill rate
DPLL phase lock detector drain rate
DPLL frequency lock detector threshold level
DPLL frequency lock detector fill rate
DPLL frequency lock detector drain rate
Reference-to-Profile Assignment Control
The user can manually assign a reference to a profile or let the
device make the assignment automatically. The manual reference
profile selection register (Address 0x0503 and Address 0x0504)
is used to program whether a reference-to-profile assignment is
manual or automatic. The manual reference profile selection regi-
ster is a 2-byte register partitioned into four half bytes (or nibbles).
相关PDF资料 |
PDF描述 |
|---|---|
| AD9548BCPZ-REEL7 | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| AD9549ABCPZ-REEL7 | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| AD9550BCPZ-REEL7 | IC INTEGER-N TRANSLATOR 32-LFCSP |
| AD9551BCPZ | IC CLOCK GEN MULTISERV 40-LFCSP |
| AD9552BCPZ-REEL7 | IC PLL CLOCK GEN LP 32LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9548 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer |
| AD9548/PCBZ | 功能描述:BOARD EVAL FOR AD9548 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9548/PCBZ | 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board |
| AD9548BCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
| AD9548BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。