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| 型号： | AD9547BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/104页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9547 Mask Change 20/Oct/2010 |
| 标准包装： | 750 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750kHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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AD9547
Data Sheet
Rev. E | Page 16 of 104
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
20
I
Differential
input
CLKINN
Clock DistributionInput. In standard operating mode, this pin is connected to
the filteredDACOUTNoutput.Thisinternally biasedinputis typically ac-coupled,
and, when configured as such, can accept any differential signal with a single-
ended swing of at least 400 mV.
21
I
Differential
input
CLKINP
Clock DistributionInput. In standard operating mode, this pin is connected to
the filteredDACOUTP output.
23
I
Power
AVDD
1.8 V Analog (Input Receiver) Power Supply.
24
O
Current set
resistor
OUT_RSET
Connect an optional 3.12 k resistor from this pin to ground (see the Output
25, 31
I
Power
AVDD3
Analog Supply for Output Driver. These pins are normally 3.3 V but can be
1.8 V. Pin 25 powers OUT0. Pin 31 powers OUT1. Apply power to these pins
even if the corresponding outputs (OUT0P/OUT0N, OUT1P/OUT1N) are not
used. See the Power Supply Partitions section.
26
O
LVPECL,
LVDS, or
CMOS
OUT0P
Output 0. This output can be configured as LVPECL, LVDS, or single-ended
CMOS. LVPECL and LVDS operationrequire a 3.3 V output driver power
supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output
driver power supply.
27
O
LVPECL,
LVDS, or
CMOS
OUT0N
Complementary Output 0. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
28, 32
I
Power
AVDD
1.8 V Analog (Output Divider) Power Supply.
29
O
LVPECL,
LVDS, or
CMOS
OUT1P
Output 1. This output can be configured as LVPECL, LVDS, or single-ended
CMOS. LVPECL and LVDS operationrequire a 3.3 V output driver power
supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output
driver power supply.
30
O
LVPECL,
LVDS, or
CMOS
OUT1N
Complementary Output 1. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
33
I
Power
AVDD3
3.3 V Analog (System Clock) Power Supply.
34
I
SYSCLK_VREG
System Clock Loop Filter Voltage Regulator. Connect a 0.1 μF capacitor from
this pinto ground. This pinis also the ac ground reference for the integrated
externalloopfilter ofthe SYSCLK PLL multiplier(seethe SYSCLK PLL Multiplier
section).
35
O
SYSCLK_LF
System Clock Multiplier Loop Filter. Whenusing the frequency multiplier to
drive the system clock, an external loop filter can be attached to this pin.
36, 39
I
Power
AVDD
1.8 V Analog (System Clock) Power Supply.
37
I
Differential
input
SYSCLKN
Complementary System Clock Input. Complementary signal to SYSCLKP.
SYSCLKN containsinternaldc biasingandshouldbe ac-coupledwitha 0.01μF
capacitor, except when using a crystal. When using a crystal, connect it across
SYSCLKP and SYSCLKN.
38
I
Differential
input
SYSCLKP
System Clock Input. SYSCLKP contains internal dc biasing and should be ac-
coupledwith a 0.01 μF capacitor, except when using a crystal. When using a
crystal, connect it directly across SYSCLKP and SYSCLKN. Single-ended 1.8 V
CMOS is also an option but can introduce a spur if the doubler is enabledand
the duty cycle is not 50%. When using SYSCLKP as a single-ended input,
connect a 0.01 μF capacitor from SYSCLKN to ground.
40, 41
I
TDC_VRB,
TDC_VRT
Use capacitive decouplingon these pins (see Figure 37).
42
I
Power
AVDD
1.8 V Analog (Time-to-Digital Converter) Power Supply.
43, 49
I
Power
AVDD3
3.3 V Analog (Reference Input) Power Supply.
44
I
Differential
input
REFA
Reference A Input. This internally biased input is typically ac-coupledand,
when configured as such, can accept any differential signal with a single-
endedswingofup to 3.3 V. Ifdc-coupled,input canbeLVPECL, CMOS,or LVDS.
45
I
Differential
input
REFAA
Complementary Reference A Input. Complementary signal to the input pro-
videdonPin44. The usercanconfigurethis pinas a separatesingle-endedinput.
46, 50
I
Power
AVDD
1.8 V Analog (Reference Input) Power Supply.
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相关代理商/技术参数 |
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| AD9548 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer |
| AD9548/PCBZ | 功能描述:BOARD EVAL FOR AD9548 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9548/PCBZ | 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board |
| AD9548BCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
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