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参数资料
| 型号： | AD9523BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/60页 |
| 文件大小： | 0K |
| 描述： | IC INTEGER-N CLCK GEN 72LFCSP |
| 标准包装： | 400 |
| 类型： | 时钟/频率发生器，扇出缓冲器（分配） |
| PLL： | 是 |
| 主要目的： | 以太网，光纤通道，SONET/SDH |
| 输入： | CMOS |
| 输出： | HSTL，LVCMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:14 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1GHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 72-LFCSP-VQ（10x10） |
| 包装： | 带卷 (TR) |
| 配用： | AD9523/PCBZ-ND - BOARD EVAL FOR AD9523 |
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AD9523
Data Sheet
Rev. C | Page 20 of 60
THEORY OF OPERATION
DETAILED BLOCK DIAGRAM
CHARGE
PUMP
×2
÷D1
VCXO
SWITCH-
OVER
CONTROL
÷M1
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
STATUS MONITOR
LOCK DETECT/
SERIAL PORT
ADDRESS
CONTROL
INTERFACE
(SDI AND I2C)
SCLK/SCL
SDO
SDIO/SDA
÷N2
PLL2
LDO_PLL2
LOOP
FILTER
TO SYNC
LOOP
FILTER
CHARGE
PUMP
PLL1
LOCK
DETECT
LOCK
DETECT
P
F
D
ZD_IN
PD
RESET
SYNC
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
÷D
t
EDGE
SYNC
SIGNAL
PLL1_OUT
VDD1.8_OUT[x:y]
REFA
REFB
AD9523
REF_SEL
STATUS0/
SP0
STATUS1/
SP1
EEPROM
EEPROM_SEL
LF2_EXT_CAP
LF1_EXT_CAP
REF_TEST
OSC_CTRL OSC_IN
CS
÷R
÷N1
LDO_PLL1
LDO_VCO
VDD3_OUT[x:y]
VDD3_PLL1
VDD3_PLL2
NC
VCO
P
F
D
0
843
9-
020
÷R
Figure 22. Top Level Diagram
OVERVIEW
The AD9523 is a clock generator that employs integer-N-based
phase-locked loops (PLL). The device architecture consists of
two cascaded PLL stages. The first stage, PLL1, consists of an
integer division PLL that uses an external voltage-controlled
crystal oscillator (VCXO) from 15 MHz to 250 MHz. PLL1 has
a narrow-loop bandwidth that provides initial jitter cleanup of the
input reference signal. The second stage, PLL2, is a frequency
multiplying PLL that translates the first stage output frequency
to a range of 3.6 GHz to 4.0 GHz. PLL2 incorporates an integer-
based feedback divider that enables integer frequency multipli-
cation. Programmable integer dividers (1 to 1024) follow PLL2,
establishing a final output frequency of 1 GHz or less.
The AD9523 includes reference signal processing blocks that
enable a smooth switching transition between two reference
inputs. This circuitry automatically detects the presence of the
reference input signals. If only one input is present, the device
uses it as the active reference. If both are present, one becomes
the active reference and the other becomes the backup reference.
If the active reference fails, the circuitry automatically switches
to the backup reference (if available), making it the new active
reference. A register setting determines what action to take if
the failed reference is once again available: either stay on
Reference B or revert to Reference A. If neither reference can
be used, the AD9523 supports a holdover mode. A reference
select pin (REF_SEL, Pin 16) is available to manually select
which input reference is active (see Table 43). The accuracy of the
holdover is dependent on the external VCXO frequency
stability at half supply voltage.
Any of the divider settings are programmable via the serial
programming port, enabling a wide range of input/output
frequency ratios under program control. The dividers also
include a programmable delay to adjust timing of the output
signals, if required.
The output is compatible with LVPECL, LVDS, or HSTL logic
levels (see the Input/Output Termination Recommendations
section); however, the AD9523 is implemented only in CMOS.
The loop filters of each PLL are integrated and programmable.
Only a single external capacitor for each of the two PLL loop
filters is required.
The AD9523 operates over the extended industrial temperature
range of 40°C to +85°C.
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| AD9524 | 制造商:AD 制造商全称:Analog Devices 功能描述:Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs |
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