参数资料
| 型号： | AD9549ABCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/76页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9549A Mask Change 22/Oct/2010 |
| 标准包装： | 1 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，HSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750MHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 产品目录页面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 32 of 76
OUTPUT FREQUENCY RANGE CONTROL
Under normal operating conditions, the output frequency is
dynamically changing in response to the output of the digital
loop filter. The loop filter can steer the DDS to any frequency
between dc and fS/2 (with 48-bit resolution). However, the user
is given the option of placing limits on the tuning range of the
DDS via two 48-bit registers in the I/O register map: the FTW
upper limit and the FTW lower limit. If the tuning word input
exceeds the upper or lower frequency limit boundaries, the
tuning word is clipped to the appropriate value. The default
setting for these registers is fS/2 and dc, respectively. The
frequency word tuning limits should be used with caution
because they may make the digital loop unstable.
It may be desirable to limit the output range of the DDS to a
narrow band of frequencies (for example, to achieve better jitter
performance in conjunction with a band pass filter). See the Use
of Narrow-Band Filter for High Performance section for more
information about this feature.
06744-
038
DDS/DAC
LOOP
FILTER
PHASE
DETECTOR
REF IN
÷S
÷R
EXTERNAL
RECONSTRUCTION
FILTER
DDS/DAC
LOOP
FILTER
PHASE
DETECTOR
REF IN
÷S
÷R
EXTERNAL
RECONSTRUCTION
FILTER
FREQUENCY
LIMITER
LOW PASS
BAND PASS
Figure 38. Application of the Frequency Limiter
RECONSTRUCTION FILTER
The origin of the output clock signal produced by the AD9549 is
the combined DDS and DAC. The DAC output signal appears as
a sinusoid sampled at fS. The frequency of the sinusoid is deter-
mined by the frequency tuning word (FTW) that appears at the
input to the DDS. The DAC output is typically passed through
an external reconstruction filter that serves to remove the
artifacts of the sampling process and other spurs outside the
filter bandwidth. The signal is then brought back on-chip to
be converted to a square wave that is routed internally to the
output clock driver or the 2× DLL multiplier.
Because the DAC constitutes a sampled system, its output must
be filtered so that the analog waveform accurately represents the
digital samples supplied to the DAC input. The unfiltered DAC
output contains the desired baseband signal, which extends from
dc to the Nyquist frequency (fS/2). It also contains images of the
baseband signal that theoretically extend to infinity. Note that
the odd images (shown in Figure 39) are mirror images of the
baseband signal. Furthermore, the entire DAC output spectrum
is affected by a sin(x)/x response, which is caused by the sample-
and-hold nature of the DAC output signal.
The response of the reconstruction filter should preserve the
baseband signal (Image 0), while completely rejecting all other
images. However, a practical filter implementation typically
exhibits a relatively flat pass band that covers the desired output
frequency plus 20%, rolls off as steeply as possible, and then
maintains significant (though not complete) rejection of the
remaining images.
Because the DAC output signal serves as the feedback signal for
the digital PLL, the design of the reconstruction filter can have
a significant impact on the overall jitter performance. Hence,
good filter design and implementation techniques are important
for obtaining the best possible jitter results.
Use of Narrow-Band Filter for High Performance
A distinct advantage of the AD9549 architecture is its ability to
constrain the frequency output range of the DDS. This allows
the user to employ a narrow-band reconstruction filter instead
of the low-pass response shown in Figure 39, resulting in less
jitter on the output. For example, suppose that the nominal
output frequency of the DDS is 150 MHz. One might then
choose a 5 MHz narrow band filter centered at 150 MHz. By
using the AD9549's DDS frequency limiting feature, the user
can constrain the output frequency to 150 MHz ± 4.9 MHz
(which allows for a 100 kHz margin at the pass-band edges).
This ensures that a feedback signal is always present for the
digital PLL. Such a design is extremely difficult to implement
with conventional PLL architectures.
PRIMARY
SIGNAL
FILTER
RESPONSE
SIN(x)/x
ENVELOPE
SPURS
IMAGE 0
IMAGE 1
IMAGE 2
IMAGE 3
IMAGE 4
0
–20
–40
–60
–80
–100
MAGNITUDE
(dB)
fs/2
fs
3
fs/2
2
fs
5
fs/2
f
BASE BAND
06744-
039
Figure 39. DAC Spectrum vs. Reconstruction Filter Response
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| AD9549APCBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
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