参数资料
| 型号： | AD9551BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/40页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN MULTISERV 40-LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟发生器 |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 900MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
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AD9551
Rev. B | Page 23 of 40
4.
Determine the feedback divider values for the output PLL.
Repeat this step for each ODF when multiple ODFs exist
(for example, 35, 36, and 40, in the case of Table 17).
To calculate the feedback divider values for a given ODF, use
the following equation:
Y
X
ODF
f
IF
OUT1
=
×
Note that the left side of the equation contains variables
with known quantities. Furthermore, the values are neces-
sarily rational, so the left side is expressible as a ratio of two
integers, X and Y. The following is an example equation:
Y
X
=
×
1664
500
,
247
)
64
(
26
)
6
)(
66
(
625
6
26
64
66
625
In the context of the AD9551, X/Y is always an improper
fraction. Therefore, it is expressible as the sum of an integer,
N, and the proper fraction, R/Y (R and Y are integers).
Y
R
N
Y
X
+
=
Y
R
N
+
=
1664
500
,
247
07
80
5-
03
0
Therefore, the example yields N = 148, Y = 1664, and R =
1228. To arrive at this result, use long division to convert the
improper fraction, X/Y, to an integer (N) and a proper fraction
(R/Y). Note that dividing Y into X by means of long division
yields an integer, N, and a remainder, R. The proper fraction
has a numerator (R, the remainder) and a denominator (Y,
the divisor), as follows:
YX
N
R
–NY
= N +
X
Y
R
Y
Figure 23. Example Long Division
It is imperative to use long division to obtain the correct
results. Avoid the use of a calculator or math program
because these do not always yield correct results due to
internal rounding and/or truncation. Some calculators or
math programs may be up to the task if they can handle very
large integer operations, but such are not common.
In the example, N = 148 and R/Y = 1228/1664, which reduces
to R/Y = 307/416. These values of N, R, and Y constitute
the fol-lowing respective feedback divider values: N = 148,
FRAC = 307, and MOD = 416.
The only caveat is that N and MOD must meet the constraints
given in the Output/Input Frequency Relationship section.
In the example, FRAC is nonzero, so the division value is
an integer plus the fractional component, FRAC/MOD. This
implies that the feedback SDM is necessary as part of the feed-
back divider. If FRAC = 0, the feedback division factor is an
integer and the SDM is not required (it can be bypassed).
Although the feedback divider values obtained in this way
provide the proper feedback divide ratio to synthesize the
exact output frequency, they may not yield optimal jitter
performance at the final output. One reason for this is that
the value of MOD defines the period of the SDM, which has
a direct impact on the spurious output of the SDM. Spe-
cifically, the SDM spectrum has MOD at evenly spaced
spurs between dc and fIF. Thus, the spectral sepa-ration
(Δf) of the spurs associated with the feedback SDM is
f
MOD
f
IF
=
Δ
Because the SDM is in the feedback path of the output PLL,
these spurs appear in the output signal as spurious compo-
nents offset by Δf from fOUT1. Therefore, a small MOD value
produces relatively large spurs, with relatively large frequency
offsets from fOUT1, whereas a large MOD value produces
smaller spurs but more closely spaced to fOUT1. Clearly, the
value of MOD has a direct impact on the spurious content
(that is, jitter) at OUT1.
Generally, the largest possible MOD value yields the smallest
spurs. Thus, it is desirable to scale MOD and FRAC by the
integer part of 220 divided by the value of MOD obtained
previously. In the example, the value of MOD is 416, yielding
a scale factor of 2520 (the integer part of 220/416). A scale
factor of 2520 leads to FRAC = 307 × 2520 = 773,640, and
MOD = 416 × 2520 = 1,048,320.
However, these FRAC and MOD values are different from
those that appear in Table 14 (Y[3:0] = 0100). The reason is
that a scale factor of 1120 (instead of 2520) was found to yield
the most accept-able overall performance. A scale factor of
1120 results in the following Table 14 values: FRAC =
343,840 and MOD = 465,920.
5.
Determine the values of the REFA (or REFB) input dividers.
To calculate the feedback divider values, use the following
equation:
Y
X
f
IF
REF
=
Note that the left side of the equation contains variables
with known quantities. Furthermore, the values are neces-
sarily rational, so the left side is expressible as a ratio of two
integers, X and Y. The following is an example equation:
Y
X
=
200
,
616
712
,
867
,
14
)
237
)(
26
(
100
)
239
(
62208
26
237
239
08
.
622
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相关代理商/技术参数 |
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| AD9551BCPZ-REEL7 | 功能描述:IC CLOCK GEN TRANSLATOR 40LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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