参数资料
| 型号： | AD9551BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/40页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN MULTISERV 40-LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟发生器 |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 900MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
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AD9551
Rev. B | Page 16 of 40
THEORY OF OPERATION
OPERATING MODES
The AD9551 provides the following fundamental operating modes:
Normal mode
19.44 MHz mode
Mode selection depends on the state of the frequency selection pins
(A[3:0] and B[3:0]). If all four of the A[3:0] pins or all four of
the B[3:0] pins are Logic 1s, the 19.44 MHz mode is in effect.
Otherwise, normal mode is in effect.
Normal Mode
Normal mode offers two methods of operation. The first method
relies on the frequency selection pins to configure the device.
The second method involves the use of the serial port for device
configuration.
The first method is for applications that use one of the input/output
19.44 MHz mode selection). The advantage of this method is
that the serial port is not required. Connect the pins to the appro-
priate logic levels, and the device operates with the defined input
and output frequencies. The pin settings establish all the necessary
internal divider values. Note, however, that this method requires an
external crystal with a resonant frequency of 26 MHz.
The second method, which relies on the serial port, enables the
user to program custom divider settings to achieve input/output
frequency ratios not available via the frequency selection pins.
Furthermore, the 26 MHz constraint on the external crystal no
longer applies. Note, however, that the external pin settings still
establish the default values of the dividers. The serial port simply
enables the user to override the default settings.
19.44 MHz Mode
This special operating mode allows for input references that
operate specifically at 19.44 MHz, 38.88 MHz, or 77.76 MHz.
The 19.44 MHz mode is invoked by the frequency selection pins
and occurs when either A[3:0] = 1111b or B[3:0] = 1111b. Fur-
thermore, this mode requires an external crystal with one of the
following four possible resonant frequencies, based on the contents
of Register 0x33[5:4].
49.152 MHz
49.860 MHz
50.000 MHz
52.000 MHz
In the 19.44 MHz mode, the reference input dividers allow for
integer divide ratios of 1, 2, or 4 only, set via Register 0x1E[1:0].
Therefore, if fIN = 19.44 MHz, the divide ratio must be set to 1;
if fIN = 38.88 MHz, the divide ratio must be set to 2; and if fIN =
77.76 MHz, the divide ration must be set to 4.
Note that for applications using both REFA and REFB in the
19.44 MHz mode, the input frequencies must match.
Although the 19.44 MHz mode limits the input divide ratio to
1, 2, or 4, the user has full control of the dividers in the output
section. This includes the integer and fractional components of
the output PLL feedback divider and the final output dividers
(P0, P1, and P2), enabling the synthesis of a wide range of output
frequencies.
Note that the 19.44 MHz mode alters the configuration of the input
PLL (see the Input PLL section).
When using the 19.44 MHz mode, the loop filter in the output PLL
requires a 100 nF capacitor. Furthermore, the user must program
the output PLL charge pump current to 25 μA (via Register 0x0A).
Note that SPI port programming capability is necessary when
using 19.44 MHz mode because it requires a charge pump current
that is different from the default value.
COMPONENT BLOCKS
Input Dividers
Each reference input feeds a dedicated reference divider block.
The input dividers provide division of the reference frequency
in integer steps from 1 to 63. They provide the bulk of the fre-
quency prescaling necessary to reduce the reference frequency
to accommodate the bandwidth limitations of both the input
and output PLLs.
Input Sigma-Delta Modulators (SDM)
Each of the two input dividers is coupled with an optional, second-
order SDM, enabling fractional division of the input reference
frequency. With both integer and fractional divide capability, the
AD9551 can accept two different reference frequencies that span
a wide range of possible input frequency ratios.
A typical SDM offers fractional division in the form N + F/M,
where N is the integer part, M is the modulus, and F is the frac-
tional part (F < M). All three parameters are positive integers. The
input SDMs of the AD9551 are atypical in that they implement
fractional division in the form, N + 1/2 + F/(2M), with F being
a signed integer, and |F| < M. Note that when the SDM is in use,
the minimum integer divide value is 4.
Both SDMs have an integrated pseudorandom binary sequence
(PRBS) generator. The PRBS generator serves to suppress spurious
artifacts by adding a random component to the SDM output. By
default, the PRBS generator is active in both input SDMs, but
the user can disable the PRBS using Register 0x1E[2].
Note that in 19.44 MHz mode, the input SDMs are inactive and
unavailable.
Reference Monitor
The reference monitor verifies the presence or absence of the
prescaled REFA and REFB signals (that is, after division by the
input dividers). The status of the reference monitor guides the
activity of the synchronization and switchover control logic.
Note that the DCXO must be operational for the reference
monitor to function.
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| AD9551BCPZ-REEL7 | 功能描述:IC CLOCK GEN TRANSLATOR 40LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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| AD9552BCPZ | 制造商:Analog Devices 功能描述:IC PLL CLOCK GENERATOR 112.5MHZ LFCSP-32 |
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