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参数资料
| 型号： | AD9551BCPZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 900 MHz, OTHER CLOCK GENERATOR, QCC40 |
| 封装： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40 |
| 文件页数： | 32/40页 |
| 文件大小： | 792K |
| 代理商： | AD9551BCPZ |
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AD9551
Rev. B | Page 38 of 40
OUT1 Driver Control (Register 0x32)
Table 33.
Address
Bit
Bit Name
Description
0x32
7
OUT1 drive strength
Controls the output drive capability of the OUT1 driver.
0 = weak.
1 = strong (default).
6
OUT1 power-down
Controls power-down functionality of the OUT1 driver.
0 = OUT1 active (default).
1 = OUT1 powered down.
[5:3]
OUT1 mode control
OUT1 driver mode selection.
000 = CMOS, both pins active.
001 = CMOS, positive pin active, negative pin tristate.
010 = CMOS, positive pin tristate, negative pin active.
011 = CMOS, both pins tristate.
100 = LVDS.
101 = LVPECL (default).
110 = not used.
111 = not used.
[2:1]
OUT1 CMOS polarity
Selects the polarity of the OUT1 pins in CMOS mode.
00 = positive pin logic is true = 1, false = 0/negative pin logic is true = 0, false = 1 (default).
01 = positive pin logic is true = 1, false = 0/negative pin logic is true = 1, false = 0.
10 = positive pin logic is true = 0, false = 1/negative pin logic is true = 0, false = 1.
11 = positive pin logic is true = 0, false = 1/negative pin logic is true = 1, false = 0.
These bits are ineffective unless Bits[5:3] select CMOS mode.
0
Enable SPI control of OUT1
driver control
Controls OUT1 driver functionality.
0 = OUT1 is LVDS or LVPECL, per the OUTSEL pin (Pin 16) (default).
1 = OUT1 functionality defined by Bits[7:1].
Input PLL Control (Register 0x33)
Table 34.
Address
Bit
Bit Name
Description
0x33
7
Loop filter sample rate control
Select/bypass 8× clock divider to the digital loop filter.
0 = selected (default).
1 = bypassed.
6
Select 2× frequency divider
Select/bypass the 2× frequency divider.
0 = bypassed (default).
1 = selected.
Note that this bit is not functional in 19.44 MHz mode.
[5:4]
Select crystal frequency
Select the crystal frequency for 19.44 MHz mode.
00 = 52.000 MHz (default).
01 = 50.000 MHz.
10 = 49.860 MHz.
11 = 49.152 MHz.
Note that these bits are functional only in 19.44 MHz mode.
[3:0]
Unused
Unused.
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相关代理商/技术参数 |
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| AD9551BCPZ-REEL7 | 功能描述:IC CLOCK GEN TRANSLATOR 40LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9552 | 制造商:AD 制造商全称:Analog Devices 功能描述:Oscillator Frequency Upconverter |
| AD9552/PCBZ | 功能描述:BOARD EVALUATION FOR AD9552 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9552BCPZ | 功能描述:IC PLL CLOCK GEN LP 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9552BCPZ | 制造商:Analog Devices 功能描述:IC PLL CLOCK GENERATOR 112.5MHZ LFCSP-32 |
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