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| 型号： | AD9629BCPZRL7-65 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 65MSPS 32LFCSP |
| 标准包装： | 1,500 |
| 位数： | 12 |
| 采样率（每秒）： | 65M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 86mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
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AD9629
Rev. 0 | Page 21 of 32
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a 50% duty cycle clock
with ±5% tolerance is required to maintain optimum dynamic
performance as shown in Figure 51.
Jitter on the rising edge of the clock input can also impact dynamic
performance and should be minimized as discussed in the Jitter
Considerations section.
40
45
50
55
60
65
70
75
80
10
20
30
40
50
60
70
80
S
NR
(
d
B
F
S
)
POSITIVE DUTY CYCLE (%)
08
54
0-
07
8
Figure 51. SNR vs. Clock Duty Cycle
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNRLF) at a given input frequency (fINPUT) due to
jitter (tJRMS) can be calculated by
SNRHF = 10 log[(2π × fINPUT × tJRMS)2 + 10
]
)
10
/
(
LF
SNR
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 52.
80
75
70
65
60
55
50
45
1
10
100
1k
FREQUENCY (MHz)
S
NR
(
d
BF
S
)
0.5ps
0.2ps
0.05ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
0
854
0-
0
22
Figure 52. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9629.
To avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
For more information, see the AN-501 Application Note and the
AN-756 Application Note available on www.analog.com.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 53, the analog core power dissipated by
the AD9629 is proportional to its sample rate. The digital
power dissipation of the CMOS outputs are determined
primarily by the strength of the digital drivers and the load
on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (13, in the case of the
AD9629).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is estab-
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers
can minimize digital power consumption. The data in Figure 53
was taken using the same operating conditions as those used for
the Typical Performance Characteristics, with a 5 pF load on
each output driver.
35
40
45
50
55
60
65
70
75
80
85
10
20
30
40
50
60
70
80
ANAL
O
G
CO
RE
P
O
W
E
R
(m
W
)
CLOCK RATE (MSPS)
AD9231-20
AD9231-40
AD9231-65
AD9231-80
08
54
0-
0
79
Figure 53. Analog Core Power vs. Clock Rate
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9629BCPZRL7-80 | 功能描述:IC ADC 12BIT 80MSPS 32LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD9629XCPZ-40 | 功能描述:IC ADC 12BIT 40MSPS 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| AD9630 | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Distortion 750 MHz Closed-Loop Buffer Amp |
| AD9630AN | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Distortion 750 MHz Closed-Loop Buffer Amp |
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