参数资料
| 型号： | AD9785BSVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/64页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT 800MSPS 100TQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| 位数： | 12 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 450mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 托盘 |
| 输出数目和类型： | 2 电流，单极；2 电流，双极 |
| 采样率（每秒）： | 800M |
| 产品目录页面： | 785 (CN2011-ZH PDF) |
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AD9785/AD9787/AD9788
Rev. A | Page 29 of 64
The PLL control (PLLCTL) register comprises three bytes located at Address 0x04. These bits are routed directly to the periphery of the
digital logic. No digital functionality within the main digital block is required.
Table 14. PLL Control (PLLCTL) Register
Address
Bit
Name
Description
0x04
[23:21]
VCO Control Voltage
[2:0]
000 to 111, proportional to voltage at VCO, control voltage input (readback only). A value of
011 indicates that the VCO control voltage is centered.
[20:16]
PLL Loop Bandwidth
[4:0]
These bits control the bandwidth of the PLL filter. Increasing the value lowers the loop
bandwidth. Set to 01111 for optimal performance.
[15]
PLL enable
0: Default. With PLL off, the DAC sample clock is sourced directly by the REFCLK input.
1: With PLL on, the DAC clock is synthesized internally from the REFCLK input via the PLL
clock multiplier. See the Clock Multiplication section for details.
[14:13]
PLL VCO Divisor [1:0]
Sets the value of the VCO output divider, which determines the ratio of the VCO output
frequency to the DAC sample clock frequency, fVCO/fDACCLK.
00: fVCO/fDACCLK = 1
01: fVCO/fDACCLK = 2
10: fVCO/fDACCLK = 4
11: fVCO/fDACCLK = 8
[12:11]
PLL Loop Divisor [1:0]
Sets the value of the DACCLK divider, which determines the ratio of the DAC sample clock
frequency to the REFCLK frequency, fDACCLK/fREFCLK.
00: fDACCLK/fREFCLK = 2
01: fDACCLK/fREFCLK = 4
10: fDACCLK/fREFCLK = 8
11: fDACCLK/fREFCLK = 16
[10:8]
PLL Bias [2:0]
These bits control the VCO bias current. Set to 011 for optimal performance.
[7:2]
PLL Band Select [5:0]
These bits set the operating frequency of the VCO. For further details, refer to Table 35.
[1:0]
PLL VCO Drive [1:0]
These bits control the signal strength of the VCO output. Set to 11 for optimal performance.
The I DAC control register comprises two bytes located at Address 0x05. These bits are routed directly to the periphery of the digital
logic. No digital functionality within the main digital block is required.
Table 15. I DAC Control Register
Address
Bit
Name
Description
0x05
[15]
I DAC sleep
0: Default. If the I DAC sleep bit is cleared, the I DAC is active.
1: If the I DAC sleep bit is set, the I DAC is inactive and enters a low power state.
[14]
I DAC power-down
0: Default. If the I DAC power-down bit is cleared, the I DAC is active.
1: If the I DAC power-down bit is set, the I DAC is inactive and enters a low power state.
[13:10]
Reserved
Reserved for future use.
[9:0]
I DAC gain
adjustment
These bits are the I DAC gain adjustment bits.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9785BSVZRL | 功能描述:IC DAC 12BIT 800MSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD9785-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9785 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9785-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9785 制造商:Analog Devices 功能描述:DUAL 12B, 1GSPS D-A CONVERTER - Bulk 制造商:Analog Devices 功能描述:Digital to Analog Eval. Board |
| AD9786 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| AD9786BSV | 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP 制造商:Analog Devices 功能描述:IC 16BIT DAC SMD 9786 TQFP80 |
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